Sr Principal Application Engineer
Guide digital implementation, signoff, and flow optimization across advanced nodes down to 3nm and below using tools like Innovus, Tempus, and Genus.
Originally posted 6 November 2026 by the employer.
About the role
The Sr Principal Application Engineer serves as a technical leader within Cadence’s North America Field Applications Team, driving strategic customer engagements and deployment of EDA and Agentic-AI solutions. The role focuses on digital implementation, signoff technologies, and design convergence across advanced process nodes down to 3nm and below.
What you'll do
- Lead technical customer engagements to achieve target PPA, guiding adoption of digital implementation and signoff technologies across advanced nodes down to 3nm.
- Partner with R&D and Product Engineering to influence tool enhancements based on customer requirements.
- Drive complex benchmarks, flow optimizations, and methodology deployment for Synthesis, P&R, STA, IR Drop, and power/timing closure.
- Represent Cadence at industry forums, author technical papers, and deliver technical presentations.
What you'll need
- BS or MS in Electrical Engineering, Computer Engineering, or a related field.
- 15+ years of experience in IC design implementation and signoff.
- Deep expertise in digital design fundamentals, advanced node implementation at 3nm and below, and EDA tool ecosystems.
- Strong proficiency in scripting using Tcl, Python, or Perl for flow customization and design closure.
- Proven track record of leading technical engagements and managing large-scale technical programs.
Skills: P&R, STA, signoff, Cadence, 3nm, Tcl
More semiconductor jobs: Cadence Design Systems jobs · Field applications engineer jobs
This role has been open 0 days — well below the 43-day median for Applications FAE roles.
Applications FAE · EDA Tools
|
Open roles in category
123
|
Median days open
43 d
|
Category median salary (all employers)
$182k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cadence Design Systems | All employers we track in this specialty (123 roles · 10 employers) |
|---|---|---|
| Open roles in this specialty | 38 | 123 |
| Median days open | 29 d | 43 d (−14 d vs this employer) |
| Median salary (USD postings) | — | $182k |
Skills observed across this category: P&R, STA, signoff, Cadence, 3nm, Tcl
Who's hiring in this category
- Synopsys · 66 open roles · median 35 d
- Cadence Design Systems (this employer) · 35 open roles · median 38 d
- Keysight Technologies · 9 open roles · median 71 d
- Renesas Electronics · 6 open roles · median 84 d
- ASML · 2 open roles · median 33 d
- Amazon · 1 open role · median 37 d
How we counted: 123 open Applications FAE (EDA Tools) roles from 10 employers tracked in the SemiconductorJobs index, counted 6 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.