Sr. Principal Analog Design Engineer - Richardson, Texas, United States of America, United States
$171,000 - $296,000 USD yearly
Originally posted 23 May 2026 by the employer. Relisted by the employer on 18 September 2026.
About the role
The Sr. Principal Analog Design Engineer owns and drives the architecture and design of high-performance analog/mixed-signal IP used across multiple SoCs. This role focuses on signal chain IP (ADCs, DACs, amplifiers, sensor interfaces) or power management IP (LDOs, DC-DCs, charge pumps, bandgaps) for products developed by MIPS across industrial and automotive applications.
What you'll do
- Develop analog and mixed-signal IP covering signal chain blocks (SAR, pipeline, delta-sigma ADCs, DACs, precision amplifiers, sensor interfaces) or power management blocks (buck, boost, buck-boost DC-DCs, LDOs, bandgap references, charge pumps, POR, power monitoring). - Lead transistor-level schematic design, simulation, and verification across PVT corners in advanced CMOS technology nodes, addressing process variation, mismatch, noise, and reliability. - Support top-level integration, verification, and tape-out, leading post-silicon bring-up, characterization, and debugging in the lab. - Define architecture to meet Design For Test (DFT) requirements and document bring-up and initialization procedures. - Provide technical guidance, establish analog design and verification methodology best practices, and mentor junior engineers across the hardware engineering team.
What you'll need
- Bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, or a related field. - Minimum 16+ years of experience in analog mixed-signal design, with proven expertise from concept to silicon delivering complex analog IP blocks. - Deep understanding of CMOS analog design fundamentals, noise analysis, stability and compensation, device mismatch, variation, and low-power design techniques. - Strong knowledge of industry-standard EDA tools such as Cadence, Synopsys, Ansys, Virtuoso, and analog simulation environments. - Basic scripting and automation skills using PERL and Python. - Proven silicon bring-up and debugging skills, including familiarity with lab equipment.
Nice to have
- Experience applying ISO 26262/IEC 61508 standards throughout the development lifecycle at the semiconductor IP and SoC level. - Strong understanding of analog layout techniques. - Record of participation in industry technical events and publishing papers or patents.
Skills: I/O design, interface standards, PCIe, DDR, signal integrity
This role has been open 122 days — well above the 71-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
238
|
Median days open
71 d
|
Median salary
$177k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | GlobalFoundries | All employers we track in this specialty (238 roles · 47 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 238 |
| Open roles in the wider Analog & Mixed-Signal family | 12 | 1443 · 108 employers |
| Median days open | 122 d | 71 d (+51 d vs this employer) |
| Median salary (USD postings) | — | $177k |
Skills observed across this category: I/O design, interface standards, PCIe, DDR, signal integrity
Who's hiring in this category
- Synopsys · 35 open roles · median 37 d
- AMD · 27 open roles · median 41 d
- Qualcomm · 21 open roles · median 65 d
- Cadence Design Systems · 20 open roles · median 147 d
- Micron Technology · 15 open roles · median 38 d
- Apple · 9 open roles · median 24 d
How we counted: 238 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 47 employers tracked in the SemiconductorJobs index, counted 23 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.