PLL Design/ Integration Sr Staff Engineer - CA, San Jose, United States
Originally posted 21 October 2026 by the employer.
About the role
Lead and contribute to the design, integration, and characterization of Phase-Locked Loops (PLLs) for FPGA products within the AECG Fabric team. The global Clock/PLL team implements programmable clocking solutions across AMD's Adaptive Embedded Computing portfolio.
What you'll do
- Architect and integrate analog/mixed-signal PLL building blocks including VCOs, charge pumps, dividers, PFDs, Loop Filters, LDOs, Phase Interpolators, and High Speed Dividers into FPGA products. - Lead the integration of PLL topologies including integer-N, fractional-N, and all-digital/ADPLL architectures to meet power, area, jitter, and frequency range specifications. - Address advanced node challenges such as self-heating, electromigration, voltage-controlled oscillator linearization, and device-level noise optimization. - Supervise and verify layouts produced by physical design engineers to ensure floorplanning, matching, and parasitic minimization. - Lead PLL bring up in the lab and execute performance characterization with laboratory equipment. - Conduct system-level simulations and validation for PLL IP integration in FPGA environments using Vivado or equivalent flows.
What you'll need
- Bachelor's degree with relevant industry experience or Master's degree in Electrical & Electronics Engineering. - Experience with analog and digital IP integration, including PLLs, LDOs, and Phase Interpolators. - Understanding of silicon processes, packaging technologies, device physics, reliability, and silicon chip manufacturing. - Hands-on experience with post-silicon validation, characterization, and lab equipment.
Nice to have
- Experience designing fractional-N PLLs, All-Digital PLLs (ADPLL), and/or sub-sampling PLLs. - Familiarity with fundamental analog building blocks such as LDOs, bias generators, and operational amplifiers. - Background in digital design, digital verification, and SystemVerilog modeling. - Knowledge of clock synthesis and recovery techniques, including PLLs, DLLs, and CDRs.
Skills: PLL, VCO, jitter, ADPLL, clocking