$134,500 - $201,700 USD yearly
Originally posted 9 November 2026 by the employer.
About the role
As a Sr. Physical Design Engineer at Qualcomm, you will define, model, design, optimize, verify, validate, implement, and document IP (block/SoC) development for high-performance, low-power products.
What you'll do
- Apply ASIC engineering knowledge to define, model, design, optimize, verify, validate, implement, and document block- and SoC-level IP.
- Create architectures, circuit specifications, logic designs, and system simulations based on system-level requirements.
- Collaborate across hardware and software architecture teams to define and execute implementation strategies meeting system requirements.
- Evaluate all aspects of process flow from high-level design to synthesis, place and route, timing and power analysis, and verification.
- Utilize EDA tools and flows, including RTL to GDS Flow and Virtuoso, to execute block, SoC, or IC package designs.
- Author detailed technical documentation for EDA, IP, and ASIC projects.
What you'll need
- Bachelor's degree in Science, Engineering, or a related field with 2+ years of ASIC design, verification, validation, integration, or related experience (or a Master's degree with 1+ year of experience, or a PhD).
- Hands-on experience working across ASIC development and implementation flows.
- Demonstrated ability to work independently with minimal supervision on multi-step design tasks.
Nice to have
- Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science.
- 3 years of ASIC design, verification, validation, integration, or related work experience.
- 2 years of experience with architecture and design tools.
- 2 years of experience with scripting tools and programming languages.
- 2 years of experience with design verification methods.
Skills: ASIC, synthesis, place and route, timing, RTL to GDS Flow
More semiconductor jobs: Qualcomm jobs · Physical design jobs · Santa Clara jobs
First seen in our index 0 days ago, well below the 61-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
713
|
Median days since first seen
61 d
|
Category median salary (all employers)
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (713 roles · 87 employers) |
|---|---|---|
| Open roles in this specialty | 106 | 713 |
| Open roles in the wider Physical Implementation family | 148 | 1614 · 117 employers |
| Median days since first seen | 61 d | 61 d (same as this employer) |
| Median salary (USD postings) | n/a | $187k |
Skills observed across this category: ASIC, synthesis, place and route, timing, RTL to GDS Flow
Who's hiring in this category
- Qualcomm (this employer) · 104 open roles · median 61 d
- AMD · 62 open roles · median 42 d
- Broadcom · 47 open roles · median 21 d
- NVIDIA · 46 open roles · median 81 d
- Synopsys · 43 open roles · median 40 d
- Intel Corporation · 32 open roles · median 32 d
How we counted: 713 open Physical Design (Physical Design) roles from 87 employers tracked in the SemiconductorJobs index, counted 10 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Physical Implementation family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.