Sr. Memory Validation Engineer - US Headquarters, United States
$152,000 - $179,000 USD yearly
Originally posted 18 September 2026 by the employer — open 1 day.
About the role
This role involves owning the data and automation layer for memory subsystems, building test infrastructure, and feeding insights back into the design of memory controllers. You will focus on silicon bring-up and automation to improve memory subsystem stability and reliability.
What you'll do
- Own, develop, maintain, and tune memory training and calibration code for LPDDR5/5X and LPDDR6.
- Collect and analyze memory subsystem data from lab testing, customer platforms, and internal validation systems.
- Build automation for memory stability testing, performance characterization, speed binning, and regression analysis.
- Debug real customer issues alongside field teams and internal engineering groups, driving problems from first report to root cause to closure.
- Turn system behavior and failure analysis into insight that measurably improves memory controller robustness and performance.
- Support silicon bring-up, qualification, and production readiness for memory subsystems.
What you'll need
- 4+ years in memory validation, memory controller design, or SoC validation.
- Hands-on experience with LPDDR5/5X and LPDDR6, and working familiarity with JEDEC specifications.
- Experience owning or contributing to memory training and calibration code, with C/firmware skills.
- Strong Python (or equivalent) for test automation and data analysis.
- Practical debug skills on real hardware, including bench instrumentation, protocol analyzers, logic analyzers, and boot and stability failure triage.
- Comfort with data at scale to find signals in shmoo, margining, or regression results.
- Ability to work directly with customers and cross-functional teams under time pressure.
Nice to have
- Silicon bring-up or post-silicon validation experience on a production program.
- Signal integrity fundamentals: eye diagrams, jitter, and timing margin analysis on high-speed interfaces.
- Experience with low-power state validation (self-refresh, power-down, DVFS-style transitions).
- Statistical analysis, ML, or dashboarding experience applied to hardware validation data.
- Firmware or driver-level exposure to the memory stack.
Skills: memory validation, LPDDR5/5X, LPDDR6, silicon bring-up, debug, test automation
This role has been open 1 day — well below the 52-day median for Post-Silicon Validation roles.
Post-Silicon Validation · Silicon Validation
|
Open roles in category
314
|
Median days open
52 d
|
Median salary
$167k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Ambarella | All employers we track in this specialty (314 roles · 61 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 314 |
| Open roles in the wider Silicon Validation & Test family | 1 | 2024 · 111 employers |
| Median days open | 1 d | 52 d (−51 d vs this employer) |
| Median salary (USD postings) | — | $167k |
Skills observed across this category: memory validation, LPDDR5/5X, LPDDR6, silicon bring-up, debug, test automation
Who's hiring in this category
- AMD · 49 open roles · median 45 d
- Micron Technology · 26 open roles · median 23 d
- Qualcomm · 25 open roles · median 80 d
- Graphcore · 19 open roles · median 95 d
- Microchip Technology · 18 open roles · median 48 d
- NVIDIA · 18 open roles · median 17 d
How we counted: 314 open Post-Silicon Validation (Silicon Validation) roles from 61 employers tracked in the SemiconductorJobs index, counted 20 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.