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Lattice Semiconductor

Sr. Memory Designer - San Jose, CA, United States

Lattice Semiconductor San Jose, CA, United States 1 month ago
Digital Design & SoC Architecture

$248,400 USD yearly

Originally posted 1 September 2026 by the employer.

About the role

As Sr. Memory Designer, you will lead the design and development of custom circuits for high-speed and low-power SRAM and low-power configuration RAM (CRAM).

What you'll do

  • Lead the design and development of custom circuits for high-speed and low-power SRAM and low-power configuration RAM (CRAM).
  • Develop memory architectures and implement them in FinFET and nanometer CMOS technologies.
  • Perform schematic capture, simulation, and margin verification of major memory blocks.
  • Oversee layout planning and ensure tight pitch-matched memory layout designs.
  • Work closely with architecture and design teams to define memory PPA and yield targets.
  • Manage the full embedded memory design flow, including architecture, circuit design, physical implementation, compiler usage, characterization, timing, and model generation.

What you'll need

  • Bachelor’s degree in electrical engineering, or a related field.
  • Over 10 years of experience in memory design, verification, validation, and integration.
  • Strong knowledge of custom memory design, high speed, low power, and custom memory design for configuration of FPGA.
  • Expertise in high-performance and low-power design techniques.
  • Familiarity with variation-aware design in advanced semiconductor technologies.

Nice to have

  • Experience with large density memory cell design for high yield.
  • Knowledge of semiconductor device fundamentals.

Skills: SoC Chip Lead, MCMs, 2.5D/3D advanced packaging, chiplet-based architectures, chip tapeout, system-level functional and performance modeling

Market context

This role has been open 33 days — well below the 75-day median for SoC/Chip Architecture roles.

SoC/Chip Architecture · SOC Architecture

Open roles in category
442
Median days open
75 d
Median salary
$236k
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
How Lattice Semiconductor compares in SoC/Chip Architecture hiring
Metric Lattice Semiconductor All employers we track in this specialty (442 roles · 64 employers)
Open roles in this specialty 1 442
Open roles in the wider Digital Design & Verification family 16 3109 · 114 employers
Median days open 33 d 75 d (−42 d vs this employer)
Median salary (USD postings) — $236k

Skills observed across this category: SoC Chip Lead, MCMs, 2.5D/3D advanced packaging, chiplet-based architectures, chip tapeout, system-level functional and performance modeling

Who's hiring in this category

  • Qualcomm · 71 open roles · median 82 d
  • NVIDIA · 57 open roles · median 59 d
  • AMD · 36 open roles · median 61 d
  • Arm Holdings · 27 open roles · median 102 d
  • Renesas Electronics · 22 open roles · median 59 d
  • NXP Semiconductors · 20 open roles · median 104 d

How we counted: 442 open SoC/Chip Architecture (SOC Architecture) roles from 64 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.

Apply now
San Jose, CA, United States
On-site
$248,400 USD yearly
1 month ago

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