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Lattice Semiconductor

Sr. Memory Designer

Lattice Semiconductor San Jose, CA, United States Full-time 2 months ago
Digital Design & SoC Architecture

$248,400 USD yearly

Originally posted 1 September 2026 by the employer.

About the role

This role leads custom circuit design and development for high-speed, low-power SRAM and low-power configuration RAM (CRAM). You will drive the full embedded memory design flow and implement memory architectures in advanced semiconductor technologies, including FinFET and nanometer CMOS.

What you'll do

  • Lead the design and development of custom circuits for high-speed and low-power SRAM and low-power configuration RAM (CRAM).
  • Develop memory architectures and implement them in advanced semiconductor technologies, including FinFET and nanometer CMOS.
  • Perform schematic capture, simulation, and margin verification of major memory blocks.
  • Oversee layout planning and ensure tight pitch-matched memory layout designs.
  • Work with architecture and design teams to define memory PPA (Performance, Power, Area) and yield targets.
  • Manage the full embedded memory design flow, including architecture, circuit design, physical implementation, compiler usage, characterization, timing, and model generation.

What you'll need

  • Bachelor’s degree in Electrical Engineering or a related field.
  • Over 10 years of experience in memory design, verification, validation, and integration.
  • Strong knowledge of custom memory design for high speed, low power, and FPGA configuration.
  • Expertise in high-performance and low-power design techniques.
  • Familiarity with variation-aware design in advanced semiconductor technologies.

Nice to have

  • Master’s or PhD in Electrical Engineering or a related field.
  • Experience with large density memory cell design for high yield.
  • Knowledge of semiconductor device fundamentals.

Skills: SoC Chip Lead, MCMs, 2.5D/3D advanced packaging, chiplet-based architectures, chip tapeout, system-level functional and performance modeling

More semiconductor jobs: SoC design jobs · San Jose jobs

Market context

This role has been open 69 days — well below the 81-day median for SoC/Chip Architecture roles.

SoC/Chip Architecture · SOC Architecture

Open roles in category
489
Median days open
81 d
Category median salary (all employers)
$230k
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
How Lattice Semiconductor compares in SoC/Chip Architecture hiring
Metric Lattice Semiconductor All employers we track in this specialty (489 roles · 67 employers)
Open roles in this specialty 3 489
Open roles in the wider Digital Design & Verification family 34 3523 · 120 employers
Median days open 33 d 81 d (−48 d vs this employer)
Median salary (USD postings) — $230k

Skills observed across this category: SoC Chip Lead, MCMs, 2.5D/3D advanced packaging, chiplet-based architectures, chip tapeout, system-level functional and performance modeling

Who's hiring in this category

  • Qualcomm · 79 open roles · median 91 d
  • NVIDIA · 67 open roles · median 83 d
  • AMD · 39 open roles · median 70 d
  • Arm Holdings · 29 open roles · median 13 d
  • Apple · 28 open roles · median 14 d
  • Micron Technology · 21 open roles · median 109 d

How we counted: 489 open SoC/Chip Architecture (SOC Architecture) roles from 67 employers tracked in the SemiconductorJobs index, counted 10 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.

Apply now
San Jose, CA, United States
On-site
Full-time
$248,400 USD yearly
2 months ago

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