CPU IP Design & Verification Intern – RISC-V Processor Development (Summer 2027)
$41,600 - $83,200 USD yearly
Work on RISC-V processor IP design and verification within the MIPS CPU IP Engineering organization.
Originally posted 10 November 2026 by the employer.
About the role
Join the MIPS CPU IP Engineering organization for hands-on experience in the design and verification of advanced RISC-V processor IP. You will collaborate on CPU microarchitecture, SystemVerilog RTL implementation, functional verification, and performance analysis.
What you'll do
- Support RISC-V CPU microarchitecture and SystemVerilog RTL design for instruction fetch, decode, execution, caches, and memory interfaces.
- Develop verification tests, assertions, checkers, and functional coverage for CPU features.
- Run CPU simulations and regressions, debugging failures using logs, architectural traces, and waveforms.
- Support CPU power, performance, and area analysis and optimization.
- Develop Python, C/C++, or scripting-based automation to improve verification, regression, and debug productivity.
What you'll need
- Active enrollment as at least a sophomore pursuing a Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field with a minimum 3.0 GPA.
- Coursework or project experience in digital logic design and computer architecture.
- Familiarity with Verilog or SystemVerilog.
- Understanding of CPU fundamentals including pipelines, instruction execution, loads/stores, caches, and memory hierarchy.
- Programming or scripting experience with Python, C/C++, or similar languages.
- Ability to work at least 40 hours per week during the internship.
Nice to have
- Knowledge of the RISC-V Instruction Set Architecture (ISA).
- Experience with SystemVerilog/UVM, assertions, functional coverage, or constrained-random verification.
- CPU architecture, microarchitecture, FPGA, ASIC, or processor-design project experience.
- Familiarity with caches, memory subsystems, privilege modes, exceptions, interrupts, or virtual memory.
- Experience with simulation, waveform debug, Git, and Linux.
- Exposure to synthesis, lint, clock-domain crossing analysis, formal verification, or timing analysis.
- Assembly-language programming experience.
Skills: RISC-V, SystemVerilog, RTL, CPU microarchitecture, simulation
More semiconductor jobs: GlobalFoundries jobs · RTL design jobs · Austin jobs
This role has been open 0 days — well below the 64-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1096
|
Median days open
64 d
|
Category median salary (all employers)
$189k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | GlobalFoundries | All employers we track in this specialty (1096 roles · 104 employers) |
|---|---|---|
| Open roles in this specialty | 22 | 1096 |
| Open roles in the wider Digital Design & Verification family | 46 | 3521 · 120 employers |
| Median days open | 42 d | 64 d (−22 d vs this employer) |
| Median salary (USD postings) | — | $189k |
Skills observed across this category: RISC-V, SystemVerilog, RTL, CPU microarchitecture, simulation
Who's hiring in this category
- Qualcomm · 141 open roles · median 75 d
- AMD · 93 open roles · median 52 d
- Synopsys · 89 open roles · median 53 d
- NVIDIA · 47 open roles · median 66 d
- NXP Semiconductors · 45 open roles · median 109 d
- Analog Devices · 40 open roles · median 56 d
How we counted: 1096 open Digital/RTL Design (RTL Design) roles from 104 employers tracked in the SemiconductorJobs index, counted 10 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.