Sr. Engineer, Process Development - USA - City of Industry, CA, United States
$95,000 - $135,000 USD yearly
Originally posted 29 October 2026 by the employer.
InP Buried Heterostructure (BH) DFB lasers and BH Gain Chips (GC) fabrication.
About the role
The Process Engineer is responsible for developing, optimizing, and sustaining wafer fabrication processes that support yield, quality, and throughput for InP photonic device lines. The scope includes owning process modules supporting InP Buried Heterostructure (BH) DFB lasers and BH Gain Chips, as well as surface preparation and Mesa etch steps for MOCVD epitaxial regrowth.
What you'll do
- Own assigned wafer fab process modules—including photolithography, PECVD, dry etch, wet etch, and metallization—for InP BH DFB laser and BH Gain Chip production. - Develop, characterize, and optimize lithography CD and overlay control, dielectric film properties, Mesa etch profile, and surface preparation for MOCVD regrowth. - Lead root-cause investigations and corrective action for process excursions, yield loss, and drift using structured methodologies such as 8D, fishbone, and FMEA. - Define and review SPC charts, control limits, monitor strategies, and maintain Process-of-Record (POR) documentation and work instructions. - Plan and execute design of experiments (DOE), process qualifications, and NPI runs to transition new processes into volume production. - Characterize process outcomes using SEM, profilometry, ellipsometry, and TLM test structures to correlate process parameters with device performance.
What you'll need
- Master’s degree in materials science, electrical engineering, chemical engineering, physics, or a related engineering or science field. - 2 to 5 years of experience in semiconductor or photonics wafer processing, or relevant graduate research in III-V device fabrication. - Hands-on experience with one or more process areas: photolithography, PECVD, dry etch, wet etch, or metallization. - Working knowledge of semiconductor process physics and chemistry for III-V materials, including plasma and wet etch, thin film deposition, and ohmic contact formation. - Proficiency in statistical analysis, SPC, and DOE using tools such as JMP, Minitab, or Python. - Familiarity with fab metrology and characterization tools including CD-SEM, profilometer, ellipsometer, XRD, and TLM test structures.
Nice to have
- Direct III-V or InP process experience. - Experience with InP-based laser or photonic integrated circuit fabrication.
Skills: InP, MOCVD, Photolithography, Dry Etch, III-V, DFB Laser
This role has been open 0 days — well below the 49-day median for Compound Semiconductor Engineering roles.
Compound Semiconductor Engineering · Compound Semiconductor
|
Open roles in category
72
|
Median days open
49 d
|
Median salary
$120k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Semtech | All employers we track in this specialty (72 roles · 25 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 72 |
| Median days open | 106 d | 49 d (+57 d vs this employer) |
| Median salary (USD postings) | — | $120k |
Skills observed across this category: InP, MOCVD, Photolithography, Dry Etch, III-V, DFB Laser
Who's hiring in this category
- Infineon Technologies · 9 open roles · median 49 d
- MACOM · 8 open roles · median 1 d
- Coherent Corp · 7 open roles · median 127 d
- Lumentum · 6 open roles · median 114 d
- Texas Instruments · 5 open roles · median 47 d
- STMicroelectronics · 4 open roles · median 74 d
How we counted: 72 open Compound Semiconductor Engineering (Compound Semiconductor) roles from 25 employers tracked in the SemiconductorJobs index, counted 29 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.