SR ENGINEER, DPG ARCHITECTURE STRATEGY - San Jose, CA, United States
$170,604 - $238,000 USD yearly
Originally posted 19 August 2026 by the employer.
Develop memory controller models and simulation methodologies for new LPDRAM features.
About the role
As an SR Engineer, DPG Architecture Strategy, you will be responsible for developing memory controller models and simulation methodologies to enable new DRAM features. This role involves developing hardware models for LPDRAM features and related validation test benches.
What you'll do
- Develop hardware models for DRAM features and related validation test benches.
- Develop memory controller models, including request scheduling and address mapping.
- Develop automation test scripts using Python to improve simulation methodologies.
- Develop new DRAM technology changes per spec and state machine, and their validation test bench.
- Identify system data, hardware, or software components required to meet user needs.
- Communicate project information through presentations, technical reports, or white papers.
What you'll need
- Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, Computer Science, or related field.
- C/C++ or Python proficiency.
- Debugging interfaces, including GDB and PDB.
- LPDRAM technology knowledge.
- Computer Architecture expertise.
- Memory controller and Cache policy understanding.
- Simulation methodologies experience.
Skills: computer architecture, memory controller, cache policy, LPDRAM technology, simulation methodologies
This role has been open 58 days — well below the 80-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
468
|
Median days open
80 d
|
Median salary
$236k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (468 roles · 65 employers) |
|---|---|---|
| Open roles in this specialty | 22 | 468 |
| Open roles in the wider Digital Design & Verification family | 103 | 3198 · 115 employers |
| Median days open | 106 d | 80 d (+26 d vs this employer) |
| Median salary (USD postings) | — | $236k |
Skills observed across this category: computer architecture, memory controller, cache policy, LPDRAM technology, simulation methodologies
Who's hiring in this category
- Qualcomm · 71 open roles · median 86 d
- NVIDIA · 56 open roles · median 69 d
- Apple · 36 open roles · median 10 d
- AMD · 35 open roles · median 65 d
- Arm Holdings · 27 open roles · median 113 d
- NXP Semiconductors · 21 open roles · median 115 d
How we counted: 468 open SoC/Chip Architecture (SOC Architecture) roles from 65 employers tracked in the SemiconductorJobs index, counted 16 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.