SR Design Verification Engineer - CA, Santa Clara, United States
$124,040 - $212,640 USD yearly
Originally posted 8 June 2026 by the employer.
About the role
As a Design Verification Engineer in AMD’s Network Technologies Solutions Group (NTSG), you will drive verification closure on complex, high-performance ASIC designs. The team develops distributed services platforms and high-performance DPU technology for data center environments.
What you'll do
- Develop UVM-based testbench architectures, stimulus generators, agents, BFMs, scoreboards, checkers, assertions, and functional coverage models for IP, subsystem, and SoC-level verification. - Drive test plan creation, feature mapping, regression triage, and coverage strategy for complex networking and data-path IP. - Root-cause architectural, functional, and performance failures across RTL, testbench, and interfaces including PCIe, DDR, and Ethernet. - Use simulation, debug, and analysis tools such as VCS, Verdi, and DVE to optimize coverage closure and sign-off methodology. - Enhance verification infrastructure and automation scripts using Python, Tcl, Shell, or Make. - Collaborate with RTL design, architecture, validation, firmware, and emulation/HAPS teams while mentoring junior verification engineers.
What you'll need
- Bachelor’s Degree in Electrical/Computer Engineering or a related field. - Expert-level knowledge of SystemVerilog and UVM. - Hands-on experience with SystemVerilog simulators (such as VCS) and waveform debuggers (such as Verdi/DVE). - Proven experience verifying complex IP/subsystems using test plans, coverage metrics, and constrained-random methodologies. - Working knowledge of industry protocols such as PCIe, AXI, Ethernet, DDR, or DMA engines. - Scripting proficiency in Python, Perl, Shell, Tcl, or equivalent for testbench automation.
Nice to have
- Master’s Degree in Electrical/Computer Engineering or a related field. - Experience with performance verification, power-aware verification (UPF), or formal verification. - Familiarity with FPGA/HAPS-based validation and acceleration flows. - Understanding of networking or high-speed I/O pipelines. - Exposure to architectural modeling or C/C++ reference models.
Skills: UVM, SystemVerilog, testbench, PCIe, Ethernet
This role has been open 136 days — well above the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1254
|
Median days open
64 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (1254 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 94 | 1254 |
| Open roles in the wider Digital Design & Verification family | 255 | 3322 · 115 employers |
| Median days open | 53 d | 64 d (−11 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: UVM, SystemVerilog, testbench, PCIe, Ethernet
Who's hiring in this category
- Qualcomm · 120 open roles · median 43 d
- AMD (this employer) · 94 open roles · median 53 d
- NVIDIA · 84 open roles · median 65 d
- Synopsys · 67 open roles · median 39 d
- SiFive · 55 open roles · median 81 d
- Cadence Design Systems · 52 open roles · median 123 d
How we counted: 1254 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 24 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.