Sr. ASIC Emulation Engineer – HW&SW , Amazon Leo - Austin, Texas, United States
Originally posted 28 August 2026 by the employer.
This role focuses on enabling platform-level verification for Leo's modems.
About the role
As an Emulation Engineer, you will be part of a diverse team enabling platform level verification deploying Leo's modems.
What you'll do
- Build and bring-up emulation models for complex SOC designs
- Develop and maintain emulation environments and methodologies
- Debug complex hardware issues using emulation platforms
- Develop and maintain C++ based emulation testbench framework
- Create and execute verification test plans
- Interface with cross-functional teams including RTL, verification and silicon validation engineers to validate designs on emulation platforms
What you'll need
- Experience defining the emulation bring up environment for ASIC and system level emulation
- Experience participating in the design, verification and bring-up of IPs in Emulation
- Ability to write relevant scripts, develop bare metal code, debug code, test benches, and test harnesses
- Experience working closely with multi-disciplinary groups such as architecture, systems, design, verification, post-si, and board level teams
- Must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum
Skills: emulation models, SOC designs, emulation environments, C++ testbench, verification test plans
This role has been open 47 days — well below the 65-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1192
|
Median days open
65 d
|
Median salary
$186k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Amazon | All employers we track in this specialty (1192 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 15 | 1192 |
| Open roles in the wider Digital Design & Verification family | 28 | 3192 · 115 employers |
| Median days open | 28 d | 65 d (−37 d vs this employer) |
| Median salary (USD postings) | — | $186k |
Skills observed across this category: emulation models, SOC designs, emulation environments, C++ testbench, verification test plans
Who's hiring in this category
- Qualcomm · 106 open roles · median 42 d
- AMD · 99 open roles · median 55 d
- NVIDIA · 82 open roles · median 57 d
- Synopsys · 63 open roles · median 30 d
- SiFive · 54 open roles · median 72 d
- Cadence Design Systems · 50 open roles · median 114 d
How we counted: 1192 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.