Software Engineer – High-Speed SerDes

About the role

This role involves leading the development, bring-up, validation, and optimization of high-speed interfaces, specifically focusing on 224 Gb/s-per-lane Ethernet SerDes, PCI Express, and UCIe chiplet interconnects in advanced networking and compute silicon.

What you'll do

• Develop embedded software and firmware for configuring, initializing, calibrating, and monitoring high-speed SerDes PHYs.
• Lead bring-up and optimization of 224G PAM4 SerDes used in Ethernet switch, networking, and accelerator products.
• Develop software support for PCIe SerDes, including link initialization, training, equalization, lane management, error recovery, and diagnostics.
• Develop software support for UCIe die-to-die interfaces, including PHY initialization, link training, lane repair, health monitoring, and failure analysis.
• Implement SerDes adaptation and calibration workflows, including Transmitter amplitude tuning, Receiver CTLE/VGA/DFE/CDR configuration, and Adaptive equalization.
• Create automated characterization and production-test software for PRBS generation/checking, BER measurement, Eye scans, and Jitter/signal-margin analysis.

What you'll need

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 10 or more years of experience in SerDes firmware, PHY software, silicon bring-up, or high-speed interface validation.
• Deep understanding of high-speed serial-link fundamentals, including PAM4 and NRZ signaling, Channel loss, Jitter, Noise, Crosstalk, Reflections, and Clock/Data Recovery.
• Hands-on experience bringing up and debugging at least one advanced SerDes generation, preferably 112G or 224G PAM4.
• Strong experience with Ethernet SerDes and IEEE 802.3 link training, PCIe Gen5/Gen6 or later-generation PHYs, or UCIe/other high-speed die-to-die interface.
• Strong embedded programming skills in C and C++.

Nice to have

• Experience with 224G-per-lane Ethernet PHYs and 800G, 1.6T, or higher-speed Ethernet systems.
• Experience with PCIe 6.x or PCIe 7.0, including PAM4 signaling, FLIT mode, FEC, and lane margining.
• Experience with UCIe PHY and adapter-layer bring-up in multi-die or chiplet-based systems.
• Familiarity with long-reach, medium-reach, short-reach, very-short-reach, and die-to-die SerDes channels.
• Experience integrating third-party SerDes IP into an ASIC or SoC.
• Familiarity with IEEE 802.3, PCI-SIG, and UCIe Consortium specifications.

Skills: embedded software, firmware, SerDes PHYs, PCIe, UCIe, PAM4

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