SoC Validation Engineer – Power Management
$164,470 - $269,100 USD yearly
Originally posted 6 November 2026 by the employer.
About the role
Intel is seeking an SoC Validation Engineer to join the Power Management Validation team within the Data Center Group. In this role, you will validate power management architectures and features across complex SoC designs, including DVFS, power gating, reset flows, and low-power states.
What you'll do
- Develop and execute comprehensive validation plans to verify power management features against architectural and functional specifications.
- Design, develop, and maintain validation environments, automated test content, and debug infrastructure using SystemVerilog, UVM, simulation, and emulation platforms.
- Validate critical power management features including Dynamic Voltage and Frequency Scaling (DVFS), power gating, clock gating, low-power states, reset flows, thermal management, and telemetry logic.
- Execute simulation and emulation workloads, analyze validation results, and examine coverage metrics to resolve design issues early.
- Lead root cause analysis and debug of complex design issues in collaboration with architecture, RTL design, and verification teams.
- Build and maintain automation frameworks, regression environments, dashboards, and data analysis tools to increase validation efficiency.
What you'll need
- Bachelor's with 6+ years, Master's with 4+ years, or PhD with 2+ years in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
- 10+ years of experience in pre-silicon validation, functional validation, design verification, or silicon validation.
- Strong understanding of digital design fundamentals, computer architecture, and SoC design concepts.
- Strong knowledge of SystemVerilog and UVM-based validation methodologies.
- Experience with simulation or emulation environments, debugging, and root-cause analysis skills.
- Proficiency in Python, Perl, Shell, or similar scripting languages.
Nice to have
- Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- Experience validating power management features in complex SoC designs, such as Dynamic Voltage and Frequency Scaling (DVFS), power gating, clock gating, low-power state management, reset and power sequencing, or thermal management.
- Experience developing validation plans, test content, and coverage-driven validation strategies.
- Experience in assertion-based verification, formal verification, or advanced validation automation techniques.
- Experience in reset validation, power state validation, telemetry feature validation, or low-power verification methodologies.
- Experience leveraging AI and advanced analytics to improve validation productivity and quality.
Skills: SystemVerilog, UVM, power management, DVFS, simulation
More semiconductor jobs: Intel Corporation jobs · Verification engineer jobs
First seen in our index 7 days ago, well below the 59-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1412
|
Median days since first seen
59 d
|
Category median salary (all employers)
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Intel Corporation | All employers we track in this specialty (1412 roles · 101 employers) |
|---|---|---|
| Open roles in this specialty | 47 | 1412 |
| Open roles in the wider Digital Design & Verification family | 114 | 3617 · 122 employers |
| Median days since first seen | 29 d | 59 d (+30 d vs this employer) |
| Median salary (USD postings) | n/a | $185k |
Skills observed across this category: SystemVerilog, UVM, power management, DVFS, simulation
Who's hiring in this category
- Qualcomm · 138 open roles · median 52 d
- NVIDIA · 109 open roles · median 74 d
- Apple · 107 open roles · median 17 d
- Synopsys · 90 open roles · median 53 d
- AMD · 81 open roles · median 65 d
- SiFive · 57 open roles · median 72 d
How we counted: 1412 open Design Verification (Design Verification) roles from 101 employers tracked in the SemiconductorJobs index, counted 14 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Digital Design & Verification family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.