SoC RTL Design - Sr Staff

Originally posted 17 September 2026 by the employer — open 3 days.

About the role

This role focuses on SoC RTL design, specifically performing RTL quality signoff and integration for complex designs.

What you'll do

• Run RTL quality signoff using Spyglass for LINT, CDC, and RDC checks across IP blocks, subsystems, and full SoC designs.
• Develop timing constraints in SDC for synthesis and static timing analysis.
• Execute preliminary synthesis runs using Design Compiler or Fusion Compiler to validate RTL synthesizability, area, and timing feasibility.
• Perform formal equivalence checking with Formality to verify RTL-to-gate consistency.
• Integrate third-party and Synopsys IP into customer SoCs and subsystems, resolving integration issues.
• Create and modify RTL design blocks to meet customer-specific requirements.

What you'll need

• 8+ years of hands-on experience in RTL design and verification.
• Proven experience performing static verification using Spyglass or equivalent tools for LINT, CDC, and RDC analysis.
• Strong working knowledge of synthesis tools such as Design Compiler or Fusion Compiler, including constraint development and synthesis quality checks.
• Hands-on experience with Formality or equivalent formal verification tools for RTL-to-gate equivalence checking.
• Solid conceptual understanding of clock domain crossing, reset domain crossing, and common design pitfalls.
• Experience integrating IP blocks into subsystems or SoCs, including resolving interface, clocking, and protocol issues.