SoC Physical Design Formal Verification Engineer, HBM

Originally posted 12 November 2026 by the employer.

About the role

As an SoC Physical Design Formal Verification Engineer in the Heterogeneous Integration Group (HIG), you will own the formal verification signoff of advanced HBM SoC logic/base die designs as they move from RTL through synthesis, DFT insertion, place-and-route, and ECOs to tapeout. You will work closely with RTL design, physical design, DFT, low-power, and STA teams to ensure implementation preserves functional intent and power intent.

What you'll do

• Own formal equivalence checking (LEC) for HBM SoC blocks and full-chip across the implementation flow, including RTL-to-netlist, netlist-to-netlist, and ECO netlists.
• Develop and maintain equivalence setups handling retiming, clock gating, multibit banking, constant/unreachable register optimization, scan and MBIST insertion, and black-boxed hard IP.
• Debug non-equivalence and abort points, partnering with RTL, synthesis, DFT, and physical design teams to achieve clean signoff.
• Perform static low-power verification against UPF power intent covering isolation, level shifting, retention, power switches, and always-on connectivity.
• Drive functional ECO generation and implementation using formal ECO tools such as Conformal ECO or Formality ECO.
• Build and improve automated formal verification flows and regression infrastructure using Python, TCL, and shell.

What you'll need

• Hands-on experience with formal equivalence checking on complex SoC designs at advanced process nodes.
• Proficiency with formal verification tools such as Cadence Conformal LEC/LP/ECO, Synopsys Formality/VC LP, Siemens Questa, or equivalent.
• Solid understanding of the RTL-to-GDSII implementation flow, including synthesis, DFT insertion, placement, CTS, routing, and ECO flows.
• Experience debugging non-equivalence, aborts, and setup issues caused by synthesis optimizations like retiming, register merging, clock gating, and multibit flops.
• Working knowledge of power intent (UPF/CPF) and low-power design concepts including isolation, level shifting, retention, and power gating.
• Understanding of Verilog/SystemVerilog, gate-level netlists, and DFT structures (scan, compression, MBIST, JTAG).
• Scripting and automation skills using Python, TCL, Perl, and/or shell.

Nice to have

• Minimum 7 years of experience in a related field.
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Experience with HBM / DRAM adjacent SoC designs, or memory-subsystem-heavy SoCs.
• Experience with functional ECO generation and implementation on large hierarchical designs.
• Exposure to property-based formal verification (SVA, formal apps) or netlist-level CDC/RDC signoff.
• Familiarity with physical verification and signoff concepts such as DRC, LVS, and STA.

Skills: formal equivalence checking, LEC, Conformal, Formality, UPF

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