SoC Physical Design Engineer, PnR - San Diego, United States
Originally posted 28 July 2026 by the employer. Relisted by the employer on 24 September 2026.
Responsible for the physical implementation of design partition(s) for a highly complex SOC utilizing innovative process technology.
About the role
This role is directly responsible for the physical implementation of design partition(s) from netlist to tapeout for a highly complex SOC utilizing innovative process technology.
What you'll do
- Work with the logic design team to understand partition architecture and drive physical aspects early in the design cycle.
- Complete netlist to GDS2 implementation for partition(s) meeting schedule and design goals.
- Drive timing, physical, and electrical verification, and signoff closure for the partitions.
- Resolve and improve design and flow issues related to physical design, identify potential solutions, and drive execution.
- Drive optimization of PnR partitions to achieve best Power/Performance/Area.
What you'll need
- BS and 10+ years of relevant industry experience.
- Experience with partition level P&R implementation including floorplanning, clock and power distribution, timing closure, physical and electrical verification.
- Experience with physical design construction and analysis flows and methodology.
Nice to have
- MS in Electrical/Electronics/Computer Engineering or related field.
- Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ.
- Familiarity with process-related design issues including Design for Yield and Manufacturability and multi-vt strategies.
- Experience with industry standard tools, understanding their capabilities and underlying algorithms.
- Experience with typical SOC issues such as multiple voltage and clock domains and mixed signal block integration.
- Experience with floorplanning tools, P&R flows, global timing verification, and physical design verification flows.
Skills: partition level P&R, floorplanning, timing closure, physical verification, SOC designs
This role has been open 81 days — well above the 60-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
659
|
Median days open
60 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Apple | All employers we track in this specialty (659 roles · 80 employers) |
|---|---|---|
| Open roles in this specialty | 10 | 659 |
| Open roles in the wider Physical Implementation family | 29 | 1441 · 110 employers |
| Median days open | 27 d | 60 d (−33 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: partition level P&R, floorplanning, timing closure, physical verification, SOC designs
Who's hiring in this category
- Qualcomm · 119 open roles · median 45 d
- AMD · 63 open roles · median 24 d
- NVIDIA · 37 open roles · median 72 d
- Synopsys · 37 open roles · median 32 d
- Intel Corporation · 36 open roles · median 11 d
- Broadcom · 30 open roles · median 97 d
How we counted: 659 open Physical Design (Physical Design) roles from 80 employers tracked in the SemiconductorJobs index, counted 18 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.