Focus on customer engagements for UCIe, PCIe, or high-bandwidth D2D interconnects.
About the role
This role involves managing the operational aspects of IP and SoC architectural specification alignment through silicon and systems bringup and volume shipment milestones, ensuring customer success.
What you'll do
- Manage active customer engagements from IP and SoC architectural spec alignment through silicon and systems bringup and volume shipment milestones.
- Ensure alignment with internal engineering and ecosystem partners, including foundries, OSAT/packaging houses, EDA vendors (Synopsys, Cadence), and IP partners.
- Translate customer requirements (silicon architecture, interface specs, package form factor, delivery schedules) into internal program plans with clear owners and dates.
- Build and maintain trackers, risk registers, and executive dashboards covering each engagement.
- Drive gate reviews and weekly program syncs across internal RTL/DV, physical design, and validation teams.
- Identify and escalate risks early; propose and implement mitigations before they become schedule threats.
What you'll need
- 15+ years of technical customer management experience in semiconductor, custom silicon, or chiplet/advanced packaging environments.
- Experience interfacing with ecosystem partners, including chip development schedules, interdependencies on EDA and IP, tape-out schedules, and system bringup timelines.
- Familiarity with silicon fabrication and advanced packaging formats: CoWoS, InFO, 2.5D/3D integration, substrate/interposer-based assembly.
- Technical fluency in SoC or chiplet design flows to understand RTL milestones, DV sign-off, PD handoffs, and silicon bring-up phases.
- Proficiency with program tracking tools and spreadsheet-based trackers.
Nice to have
- Familiarity with key connectivity IPs UCIe, PCIe Gen 5/6/7+, or high-bandwidth D2D interconnect standards.
- Prior experience at an IP company, chiplet startup, merchant silicon company, or systems company.
- Background in AI/ML infrastructure silicon: accelerators, network switches, CPO-enabled platforms.
- Exposure to EDA infrastructure programs (SNPS/CDNS cloud flows).
Skills: customer engagements, silicon bringup, program plans, risk management, chiplet/advanced packaging, UCIe
More semiconductor jobs: San Jose jobs
This role has been open 41 days — well below the 54-day median for Technical Program Management roles.
Technical Program Management · SOC Architecture
|
Open roles in category
160
|
Median days open
54 d
|
Category median salary (all employers)
$220k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | TYLsemi | All employers we track in this specialty (160 roles · 48 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 160 |
| Median days open | 54 d | 54 d (same as this employer) |
| Median salary (USD postings) | — | $220k |
Skills observed across this category: customer engagements, silicon bringup, program plans, risk management, chiplet/advanced packaging, UCIe
Who's hiring in this category
- NVIDIA · 22 open roles · median 54 d
- Qualcomm · 20 open roles · median 64 d
- AMD · 19 open roles · median 32 d
- Synopsys · 14 open roles · median 53 d
- NXP Semiconductors · 7 open roles · median 48 d
- Arm Holdings · 5 open roles · median 11 d
How we counted: 160 open Technical Program Management (SOC Architecture) roles from 48 employers tracked in the SemiconductorJobs index, counted 8 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.