SoC Interconnect Technology Team Lead - San Jose, California, United States
$397,800 - $538,200 USD yearly
Originally posted 20 July 2026 by the employer.
Lead coherent and non-coherent interconnect fabric architecture utilizing AMBA AXI, ACE, and CHI protocols for complex SoCs.
About the role
This role leads the architecture, design, and execution of coherent and non-coherent interconnect solutions for complex SoCs across mobile, battery-operated, and large-scale compute platforms.
What you'll do
- Lead the architecture, microarchitecture, RTL design, and verification strategy for coherent and non-coherent interconnect fabrics. - Define system-level interconnect strategies, covering topology, Quality of Service (QoS), latency, bandwidth, and power optimization. - Collaborate with CPU, GPU, NPU, memory, and system teams to ensure integration and performance scaling across subsystems. - Own performance modeling, analysis, and bottleneck identification across diverse workloads and use cases. - Drive adoption and implementation of interconnect industry standards including AMBA AXI, ACE, and CHI. - Lead debug and root-cause analysis of system-level issues while mentoring a team of architects and engineers.
What you'll need
- 15+ years of experience in SoC architecture/design with a focus on interconnects or system fabrics. - Proven track record of delivering large-scale SoCs for mobile, battery-powered, or high-performance compute platforms. - Deep understanding of coherent interconnect protocols such as AMBA ACE, CHI, CCIX, CXL, or similar. - Strong experience with non-coherent interconnects including AXI and NoC-based fabrics. - Expertise in performance analysis, performance modeling, and system trade-offs covering latency, bandwidth, and power. - Solid knowledge of cache coherency, memory hierarchy, and system architecture, alongside experience leading cross-functional teams to tape-out.
Nice to have
- Experience with battery-optimized SoC design, including low power, DVFS, and power domains. - Familiarity with AI/ML accelerators, GPUs, or heterogeneous compute systems. - Exposure to network-on-chip (NoC) design methodologies and tools. - Experience with silicon bring-up and post-silicon validation.
Skills: interconnect fabrics, QoS, latency, AXI/ACE/CHI, cache coherency, performance modeling
This role has been open 90 days — well above the 78-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
472
|
Median days open
78 d
|
Median salary
$238k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Arm Holdings | All employers we track in this specialty (472 roles · 65 employers) |
|---|---|---|
| Open roles in this specialty | 27 | 472 |
| Open roles in the wider Digital Design & Verification family | 104 | 3224 · 116 employers |
| Median days open | 117 d | 78 d (+39 d vs this employer) |
| Median salary (USD postings) | — | $238k |
Skills observed across this category: interconnect fabrics, QoS, latency, AXI/ACE/CHI, cache coherency, performance modeling
Who's hiring in this category
- Qualcomm · 73 open roles · median 89 d
- NVIDIA · 56 open roles · median 70 d
- Apple · 36 open roles · median 13 d
- AMD · 34 open roles · median 61 d
- Arm Holdings (this employer) · 27 open roles · median 116 d
- Micron Technology · 22 open roles · median 108 d
How we counted: 472 open SoC/Chip Architecture (SOC Architecture) roles from 65 employers tracked in the SemiconductorJobs index, counted 19 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.