SOC Engineering, Principal Engineer
Originally posted 4 November 2026 by the employer.
About the role
As a Principal Engineer in SOC Engineering at Synopsys, you will lead subsystem and SoC design verification from planning through environment development, regression execution, and sign-off.
What you'll do
- Lead subsystem and SoC verification from requirements review and planning through regression execution, coverage closure, and sign-off.
- Architect reusable SystemVerilog/UVM environments integrating commercial VIP, processor models, register models, assertions, and scoreboards.
- Verify processor and system integration, covering boot flows, address mapping, memory access, coherency, interrupts, timers, and configuration interfaces.
- Drive verification of clock switching and gating, reset sequencing, power-state transitions, isolation, retention, and fault-management mechanisms.
- Develop directed, constrained-random, and embedded C tests for concurrent traffic, corner cases, initialization, and failure/recovery sequences.
- Lead root-cause debug across RTL, testbenches, firmware, and third-party IP while owning regression health and coverage closure.
What you'll need
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related discipline.
- 15+ years of ASIC/SoC design verification experience, including subsystem or full-chip ownership through multiple tape-outs.
- Strong SystemVerilog/UVM expertise, including constrained-random stimulus, assertions, functional coverage, scoreboards, and register models.
- Deep understanding of processor-based SoC architectures, multicore integration, memory hierarchy, coherent interconnects, AMBA interfaces, and boot flows.
- Hands-on experience verifying clock, reset, and power-control logic, as well as hardware fault-management mechanisms such as ECC/parity and error injection.
- Proficiency in embedded C/C++ for processor-driven tests, alongside scripting skills in Python, Tcl, or shell.
Nice to have
- Low-power verification using UPF and power-aware simulation.
- Lockstep verification and requirements-based verification for safety-critical designs.
- Formal verification and assertion-based verification experience.
- Emulation experience, including platform bring-up, software-driven testing, or simulation-to-emulation test reuse.
- Experience with Synopsys VCS, Verdi, VC Formal, and verification-management tools.
Skills: SystemVerilog, UVM, SoC verification, coverage closure, regressions
More semiconductor jobs: Synopsys jobs · Verification engineer jobs · Austin jobs
This role has been open 0 days — well below the 57-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1317
|
Median days open
57 d
|
Category median salary (all employers)
$184k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (1317 roles · 99 employers) |
|---|---|---|
| Open roles in this specialty | 74 | 1317 |
| Open roles in the wider Digital Design & Verification family | 191 | 3495 · 120 employers |
| Median days open | 50 d | 57 d (−7 d vs this employer) |
| Median salary (USD postings) | — | $184k |
Skills observed across this category: SystemVerilog, UVM, SoC verification, coverage closure, regressions
Who's hiring in this category
- Qualcomm · 117 open roles · median 49 d
- NVIDIA · 104 open roles · median 71 d
- Apple · 99 open roles · median 9 d
- AMD · 83 open roles · median 65 d
- Synopsys (this employer) · 73 open roles · median 50 d
- SiFive · 58 open roles · median 63 d
How we counted: 1317 open Design Verification (Design Verification) roles from 99 employers tracked in the SemiconductorJobs index, counted 5 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.