$121,800 - $182,600 USD yearly
Verify Data Center SoCs including the Qualcomm Dragonfly CPU and Qualcomm Dragonfly AI Inference Accelerator.
Originally posted 15 September 2026 by the employer.
About the role
As a Design Verification Engineer on the Data Center SoC Verification team, you will verify Data Center SoCs powering AI, high-performance computing, and cloud infrastructure. The work encompasses the Qualcomm Dragonfly CPU, Qualcomm High Bandwidth Compute (HBC), and the Qualcomm Dragonfly AI Inference Accelerator.
What you'll do
- Develop and execute comprehensive verification plans for SoC, subsystem, and IP-level features.
- Design and implement scalable SystemVerilog/UVM-based and processor-based verification environments.
- Create directed and constrained-random test scenarios, assertions (SVA), functional coverage models, and checkers.
- Debug RTL, testbench, and integration issues across multi-core CPU systems, cache coherency fabrics, DDR/HBM memory subsystems, and PCIe, CXL, and Ethernet interfaces.
- Drive functional and code coverage closure to achieve signoff.
- Support emulation and acceleration-based verification when required.
What you'll need
- Bachelor's degree in Science, Engineering, or a related field and 2+ years of ASIC design, verification, validation, integration, or related work experience (or Master's degree and 1+ year, or PhD).
- Strong technical knowledge of SystemVerilog, UVM, C, and Assertion-Based Verification (SVA).
- Experience building verification environments from architecture and specification through signoff using Coverage-Driven Verification.
- Solid understanding of computer architecture and digital design fundamentals.
- Proven experience debugging complex SoC-level issues.
Nice to have
- Experience with CPU verification, cache coherency protocols (ACE, CHI, CXL), DDR or HBM memory systems, or high-speed protocols (PCIe, Ethernet).
- Experience verifying AI/ML accelerators, security, RAS features, system performance, or system power.
- Experience with Portable Stimulus (PSS), Formal Verification, or emulation platforms (Veloce/Palladium/ZeBu).
- Experience with power-aware verification or ATE and post-silicon bring up testing.
- Proficiency in Python or scripting languages for test generation and workflow automation.
Skills: SystemVerilog, UVM, SoC, testbench, coverage
More semiconductor jobs: Qualcomm jobs · Verification engineer jobs · San Diego jobs
First seen in our index 57 days ago, below the 62-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1339
|
Median days since first seen
62 d
|
Category median salary (all employers)
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (1339 roles · 99 employers) |
|---|---|---|
| Open roles in this specialty | 129 | 1339 |
| Open roles in the wider Digital Design & Verification family | 423 | 3575 · 121 employers |
| Median days since first seen | 51 d | 62 d (+11 d vs this employer) |
| Median salary (USD postings) | n/a | $185k |
Skills observed across this category: SystemVerilog, UVM, SoC, testbench, coverage
Who's hiring in this category
- Qualcomm (this employer) · 120 open roles · median 51 d
- Apple · 108 open roles · median 15 d
- NVIDIA · 108 open roles · median 74 d
- AMD · 79 open roles · median 70 d
- Synopsys · 73 open roles · median 56 d
- SiFive · 57 open roles · median 70 d
How we counted: 1339 open Design Verification (Design Verification) roles from 99 employers tracked in the SemiconductorJobs index, counted 12 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Digital Design & Verification family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.