SoC Design Verification Engineer - CA, San Jose, United States
Originally posted 28 July 2026 by the employer.
About the role
This role is for a design verification engineer joining an SOC team focused on functional and performance verification.
What you'll do
- Develop and maintain tests for functional verification and performance verification at the core and SOC level. - Build testbench components to support IP verification. - Maintain or improve current test libraries to support IP-level testing. - Close verification quality metrics, including pass rates, code coverage, and functional coverage. - Provide technical support to cross-functional engineering teams.
What you'll need
- Bachelor's or Master's degree in Computer Engineering or Electrical Engineering. - Experience with modern processor architecture, digital design, and verification concepts. - Ability to collaborate with engineering teams across multiple sites and time zones.
Nice to have
- Understanding of SOC architecture, computer architecture, and CPU/DSP processors. - Coding skills in Verilog, SystemVerilog, UVM, C/C++, and scripting languages such as Perl or Python. - Knowledge of design flow, verification methodology, and computational logic design/verification concepts. - Experience with industry-standard protocols such as AXI, AHB, PCIe, or DDR.
Skills: UVM, SystemVerilog, functional verification, SOC architecture
This role has been open 90 days — well above the 66-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1254
|
Median days open
66 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (1254 roles · 96 employers) |
|---|---|---|
| Open roles in this specialty | 92 | 1254 |
| Open roles in the wider Digital Design & Verification family | 251 | 3346 · 116 employers |
| Median days open | 56 d | 66 d (−10 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: UVM, SystemVerilog, functional verification, SOC architecture
Who's hiring in this category
- Qualcomm · 118 open roles · median 45 d
- AMD (this employer) · 92 open roles · median 55 d
- NVIDIA · 91 open roles · median 65 d
- Synopsys · 65 open roles · median 41 d
- SiFive · 55 open roles · median 83 d
- Cadence Design Systems · 52 open roles · median 125 d
How we counted: 1254 open Design Verification (Design Verification) roles from 96 employers tracked in the SemiconductorJobs index, counted 26 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.