SOC Design Verification Engineer
$121,800 - $182,600 USD yearly
Originally posted 18 September 2026 by the employer — open 2 days.
This role focuses on verifying Qualcomm Dragonfly CPU, Qualcomm High Bandwidth Compute (HBC), and Qualcomm Dragonfly AI Inference Accelerator.
About the role
This role is for a Design Verification Engineer to join the Data Center SoC Verification team, responsible for verifying Data Center SoCs for AI, high-performance computing, and cloud infrastructure products.
What you'll do
- Develop and execute comprehensive verification plans for SoC, subsystem, and IP-level features.
- Design and implement scalable System Verilog/UVM-based and Processor-based verification environments.
- Create directed and constrained-random test scenarios to validate functionality and architectural use cases.
- Develop assertions, functional coverage models, and checkers.
- Debug RTL, testbench, and integration issues and work closely with design teams to resolve defects.
- Drive coverage closure using functional and code coverage metrics.
What you'll need
- Bachelor's or master's degree in electrical engineering, Computer Engineering, Computer Science, or related field.
- Minimum 2 years of design verification experience.
- Strong knowledge of System Verilog, UVM, C, Assertion-Based Verification (SVA), Coverage-Driven Verification, System level Use case verification.
- Experience developing verification environments from architecture/specification through signoff.
- Strong understanding of computer architecture and digital design fundamentals.
- Experience debugging complex SoC-level issues.
Nice to have
- Experience with CPU verification, Cache coherency protocols (ACE, CHI, CXL), DDR or HBM memory systems, PCIe, Ethernet, or networking protocols, AI/ML accelerator verification, Security and RAS feature verification, System Performance verification, or System Power verification.
- Experience with Portable Stimulus (PSS), Formal Verification, Emulation platforms (Veloce/Palladium/ZeBu), or Power-aware verification.
- Proficiency in Python or scripting languages for automation.
- Experience in full-chip or subsystem verification environments.
Skills: System Verilog/UVM, functional coverage, debug RTL, SoC-level issues, cache coherency
This role has been open 1 day — well below the 59-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1133
|
Median days open
59 d
|
Median salary
$188k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (1133 roles · 93 employers) |
|---|---|---|
| Open roles in this specialty | 103 | 1133 |
| Open roles in the wider Digital Design & Verification family | 375 | 3011 · 114 employers |
| Median days open | 54 d | 59 d (−5 d vs this employer) |
| Median salary (USD postings) | — | $188k |
Skills observed across this category: System Verilog/UVM, functional coverage, debug RTL, SoC-level issues, cache coherency
Who's hiring in this category
- Qualcomm (this employer) · 103 open roles · median 54 d
- AMD · 100 open roles · median 32 d
- NVIDIA · 89 open roles · median 66 d
- Synopsys · 58 open roles · median 21 d
- Micron Technology · 56 open roles · median 99 d
- SiFive · 52 open roles · median 47 d
How we counted: 1133 open Design Verification (Design Verification) roles from 93 employers tracked in the SemiconductorJobs index, counted 20 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.