$167,360 - $267,800 USD yearly
Originally posted 5 November 2026 by the employer.
About the role
This role drives the architecture, design, implementation, and optimization of complex digital logic for NAND Flash memory–based SSD controllers. You will translate system-level requirements into efficient microarchitecture and synthesizable RTL across performance, power, and area (PPA) targets.
What you'll do
- Architect, design, and implement complex RTL modules using Verilog/SystemVerilog for NAND Flash memory–based SSD controllers, including pipelines, state machines, queues, FIFOs, and DMA engines.
- Develop and optimize hardware logic for NAND command sequencing, interface control, data transfer, status handling, error recovery, and device timing management.
- Analyze and optimize RTL to meet timing, throughput, latency, power, and silicon-area targets using architectural changes, pipelining, and power-aware design techniques.
- Own RTL development through synthesis readiness, lint, clock-domain crossing (CDC), reset-domain crossing (RDC), and ASIC implementation handoff.
- Integrate or develop interfaces to ECC/LDPC engines, data-protection logic, error detection, and fault-handling subsystems.
- Support pre-silicon emulation, silicon bring-up, post-silicon debug, and root-cause analysis of hardware issues alongside verification and physical design teams.
What you'll need
- Master's or PhD degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- 3+ years of relevant experience in RTL design and ASIC development.
- Strong proficiency in Verilog/SystemVerilog designing complex, synthesizable RTL.
- Understanding of digital logic, sequential design, finite-state machines, pipelining, timing closure, and computer architecture.
- Experience with ASIC design flows including RTL simulation, lint, synthesis, static timing analysis (STA), CDC, and design integration.
- Proficiency in scripting or programming using Python, Tcl, Perl, or C/C++ to automate design tasks and analyze results.
Nice to have
- Experience designing NAND Flash memory controllers, SSD controllers, or other high-performance storage ASICs.
- Understanding of SSD architecture, Flash Translation Layer (FTL) interactions, NAND parallelism, storage data paths, and ONFI or Toggle-mode interfaces.
- Knowledge of NAND Flash reliability characteristics, error management, ECC/LDPC, bad-block handling, and read-retry mechanisms.
- Familiarity with interface protocols such as AXI, AHB, PCIe, or NVMe-related controller interfaces.
- Experience with low-power design techniques, clock gating, formal verification, hardware emulation, FPGA prototyping, or post-silicon debug.
Skills: Verilog, SystemVerilog, RTL, NAND Flash, SSD controller
More semiconductor jobs: RTL design jobs
This role has been open 0 days — well below the 62-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1084
|
Median days open
62 d
|
Category median salary (all employers)
$188k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Solidigm | All employers we track in this specialty (1084 roles · 103 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 1084 |
| Open roles in the wider Digital Design & Verification family | 5 | 3498 · 120 employers |
| Median days open | 65 d | 62 d (+3 d vs this employer) |
| Median salary (USD postings) | — | $188k |
Skills observed across this category: Verilog, SystemVerilog, RTL, NAND Flash, SSD controller
Who's hiring in this category
- Qualcomm · 140 open roles · median 72 d
- Synopsys · 92 open roles · median 49 d
- AMD · 78 open roles · median 48 d
- NVIDIA · 45 open roles · median 62 d
- NXP Semiconductors · 45 open roles · median 105 d
- Analog Devices · 41 open roles · median 52 d
How we counted: 1084 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 6 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.
