SoC Architect - CA, San Jose, United States
Originally posted 12 November 2025 by the employer. Relisted by the employer on 5 August 2026.
About the role
As an SoC Architect at AMD, you will define and drive the architecture for Adaptive SoCs across compute, memory, AI, high-speed I/O, power, clocking, and platform integration. The role focuses on silicon, package, and board-level decisions, emphasizing I/O subsystem definition, PHY integration, and platform-level interface optimization.
What you'll do
- Define and drive the architecture of SoC subsystems, including processors, memory subsystems, interconnects, AI engines, GPUs, multimedia blocks, and I/O interfaces. - Lead SoC integration strategy across control architecture, reset and boot flows, clocking architecture, power domains, security, and system manageability. - Drive early-stage architectural exploration, workload analysis, performance modeling, and specification development. - Define and evaluate system-level solutions involving analog and mixed-signal IPs, including high-speed SerDes, DDR PHYs, PCIe/CXL PHYs, and clocking subsystems. - Direct architectural decisions covering signal integrity, power integrity, board-level constraints, interface protocols, and package-board interactions. - Partner across hardware, software, validation, product planning, and system teams to deliver cohesive architecture solutions and execution plans.
What you'll need
- BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field. - Experience in heterogeneous compute systems and end-to-end SoC architecture spanning digital architecture, analog IP integration, and packaging. - Deep technical understanding of processor, memory, interconnect, and I/O subsystems. - Hands-on background in performance modeling, workload analysis, and architectural tradeoff analysis across performance, power, area, and cost.
Nice to have
- Experience leading SoC architecture for complex processor-based systems. - Understanding of analog and mixed-signal IP integration, including high-speed I/O, PHY architectures, SerDes technologies, DDR interfaces, clock generation and distribution, and power management. - Experience with board-level architecture, platform design, signal integrity, power integrity, and package interactions. - Expertise in industry-standard interfaces and protocols such as PCIe, CXL, Ethernet, USB, UCIe, DDR, LPDDR, and HBM. - Expertise in SoC control architecture, reset design, clocking strategies, power management, and system bring-up. - Knowledge of advanced process technologies and packaging approaches.
Skills: SoC architecture, Processor subsystems, Interconnect, AI, GPU, video processing
This role has been open 178 days — well below the 200-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · AI ML Hardware
|
Open roles in category
29
|
Median days open
200 d
|
Median salary
$239k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (29 roles · 11 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 29 |
| Open roles in the wider Digital Design & Verification family | 251 | 3346 · 116 employers |
| Median days open | 198 d | 200 d (−2 d vs this employer) |
| Median salary (USD postings) | — | $239k |
Skills observed across this category: SoC architecture, Processor subsystems, Interconnect, AI, GPU, video processing
Who's hiring in this category
- Qualcomm · 8 open roles · median 200 d
- NVIDIA · 7 open roles · median 196 d
- SiFive · 3 open roles · median 197 d
- AMD (this employer) · 2 open roles · median 197 d
- Infineon Technologies · 2 open roles · median 194 d
- Intel Corporation · 2 open roles · median 4 d
How we counted: 29 open SoC/Chip Architecture (AI ML Hardware) roles from 11 employers tracked in the SemiconductorJobs index, counted 26 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.