Originally posted 31 August 2026 by the employer.
This role focuses on developing Power Management ICs (PMICs).
About the role
This role involves digital architecture within the IP Center-Of-Excellence in the Analog Mixed Signal Group, focusing on digital and mixed-signal innovations across multiple business units. The architect will develop power-management (PMU) and clock management (CMU) platform IP sub-systems.
What you'll do
- Architect the digital control system for mixed-signal modules, prioritizing reusability and versatility.
- Define standard interfaces for digital and mixed-signal systems, considering future extension and reusability.
- Implement digital design architecture, low power design, synthesis, and timing analysis.
- Develop and refine micro-architecture to RTL implementation.
- Collaborate with validation teams for pre-silicon platforms, including SOCV, Emulation, and FPGA.
- Own the technical outcome for the design, verification, implementation, and execution of Power Management ICs.
What you'll need
- BS in Electrical Engineering or related with 12+ years, or MS with 10+ years of experience in leading Digital Design, Architecture, and ASIC/Mixed signal chip developments.
- Thorough understanding of the end-to-end digital design flow.
- Solid understanding of RTL design, CDC, ASIC synthesis, timing analysis, P&R, UPF, ATPG generation, and SystemVerilog (assertion).
- Solid understanding of Verilog, TCL, and Perl/Python/XML programming languages.
- Experience in developing ASIC/Mixed signal ICs for various Power Converters (multiphase converter, DC-DC PMIC/POL, AC-DC converters, LED/SiC, Motor/MOSFET drivers).
- Analog design experience and proficiency in verification, documentation, and post-silicon validation.
- In-depth knowledge of semiconductor devices like MOS transistors and BJTs.
- Knowledge with behavioral top-level modeling and mixed signal verification methodology.
- Knowledge of UNIX/Linux working environment.
- Knowledge of multiple semiconductor design tools like Matlab, Spectre, Spice, and Cadence design environment.
Nice to have
- Experience of using AI/ML in Digital Design.
- AMS simulation experience.
Skills: digital architecture, RTL, synthesis, timing analysis, power management ICs, mixed-signal
This role has been open 56 days — well below the 66-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1081
|
Median days open
66 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | onsemi | All employers we track in this specialty (1081 roles · 104 employers) |
|---|---|---|
| Open roles in this specialty | 31 | 1081 |
| Open roles in the wider Digital Design & Verification family | 59 | 3328 · 116 employers |
| Median days open | 99 d | 66 d (+33 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: digital architecture, RTL, synthesis, timing analysis, power management ICs, mixed-signal
Who's hiring in this category
- Qualcomm · 158 open roles · median 63 d
- Synopsys · 86 open roles · median 40 d
- AMD · 77 open roles · median 45 d
- Analog Devices · 49 open roles · median 56 d
- NXP Semiconductors · 44 open roles · median 100 d
- NVIDIA · 37 open roles · median 52 d
How we counted: 1081 open Digital/RTL Design (RTL Design) roles from 104 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.