Silicon Validation Intern, BS - Summer 2027 - Santa Clara, CA, United States
Originally posted 21 October 2026 by the employer.
Support post-silicon validation and silicon bring-up for rack-scale switch silicon in Santa Clara.
About the role
As a Silicon Validation Intern on the Rack Scale Switch Chip Validation team, you will support post-silicon validation of high-speed switch silicon under the guidance of senior engineers. You will contribute to testing, debugging, and automation for switching silicon used inside AI and cloud data center racks.
What you'll do
- Assist in developing, documenting, and executing test plans and test cases for switch chip validation. - Support lab-based silicon bring-up and run unit tests on hardware and firmware functionality, including emulation and verification environments. - Help collect and analyze high-speed signal and link data (such as eye diagrams, jitter, and BER) using lab test equipment. - Use diagnostics, software tools, oscilloscopes, and protocol analyzers to help isolate the root cause of failing tests. - Write and maintain scripts in Python to automate test execution, data collection, and result reporting. - Document test results, findings, and debug progress, and present them to the team.
What you'll need
- Currently pursuing a bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with an expected graduation date between Fall 2027 – Summer 2028. - Foundational understanding of digital logic, computer architecture, and high-speed I/O concepts such as SerDes and PCIe or Ethernet protocols. - Basic hands-on lab experience through coursework, research, or projects, such as hardware bring-up, testing, and debug. - Familiarity with common lab equipment such as oscilloscopes, logic analyzers, or BERTs. - Programming or scripting experience in Python, Perl, or a similar language.
Nice to have
- Coursework or project experience with PCIe, Ethernet, or other high-speed interfaces. - Exposure to the physical and protocol layers of high-speed interfaces (for example PHY, PCS, MAC). - Experience with emulation, simulation, or verification environments. - Ability to read board schematics and layouts. - Familiarity with signal integrity concepts such as eye diagrams, jitter, and BER.
Skills: Post-Silicon Validation, Silicon Bring-Up, Oscilloscopes, SerDes, Python
This role has been open 0 days — well below the 43-day median for Post-Silicon Validation roles.
Post-Silicon Validation · Silicon Validation
|
Open roles in category
420
|
Median days open
43 d
|
Median salary
$168k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Marvell Technology | All employers we track in this specialty (420 roles · 62 employers) |
|---|---|---|
| Open roles in this specialty | 13 | 420 |
| Open roles in the wider Silicon Validation & Test family | 59 | 2244 · 112 employers |
| Median days open | 20 d | 43 d (−23 d vs this employer) |
| Median salary (USD postings) | — | $168k |
Skills observed across this category: Post-Silicon Validation, Silicon Bring-Up, Oscilloscopes, SerDes, Python
Who's hiring in this category
- AMD · 57 open roles · median 47 d
- Micron Technology · 38 open roles · median 39 d
- Qualcomm · 38 open roles · median 27 d
- NVIDIA · 26 open roles · median 24 d
- Microchip Technology · 22 open roles · median 72 d
- Graphcore · 20 open roles · median 125 d
How we counted: 420 open Post-Silicon Validation (Silicon Validation) roles from 62 employers tracked in the SemiconductorJobs index, counted 21 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.