Silicon Validation Engineer - San Jose, CA, United States
$170,400 USD yearly
Originally posted 22 June 2026 by the employer.
Validate and characterize FPGA IP blocks including SERDES, DDR memory, D-PHY, and PLL from silicon arrival to production.
About the role
This role is responsible for validating building blocks in FPGA on a board level to ensure functionality and performance match design intent. FPGA building blocks validated include SERDES (PMA/PCS), DDR memory (DDR4, LPDDR4, DDR5), D-PHY, PLL, DSP, MIPI, Fabric, and I/O.
What you'll do
- Validate and characterize various IPs from silicon arrival through release to production. - Develop validation and characterization plans for IP blocks, bench hardware, and software. - Develop test logic RTL to implement validation and characterization tests. - Drive new silicon product bring-up, validation, debug, datasheet parameter characterization, and statistical data analysis. - Serve as the central resource with design, verification, manufacturing, test, quality, and marketing/applications teams from silicon arrival to product release. - Support customer issues as required to resolve problems identified post-release.
What you'll need
- 2+ years of experience with an Electrical Engineering degree focused on silicon design validation. - Expertise in high-speed SERDES interface characterization and protocol compliance testing across standards such as PCIe, Ethernet, SDI, CoaXpress, JESD204, MIPI D-PHY, MIPI CSI/DSI-2, USB, or DisplayPort/HDMI. - Expertise in high-speed board design and signal integrity evaluation and debug. - Expertise in Verilog or VHDL and design implementation using FPGA development tools. - Expertise in test automation development using Python or Perl. - Proficiency with bench characterization equipment including BERT, VNA, oscilloscopes, and protocol exercisers/analyzers. - Knowledge of statistical analysis concepts and tools such as JMP or R. - Exposure to FPGA emulation or prototyping.
Skills: silicon arrival, validation plans, product bring-up, SERDES, DDR, oscilloscopes
This role has been open 89 days — well above the 44-day median for Post-Silicon Validation roles.
Post-Silicon Validation · Silicon Validation
|
Open roles in category
411
|
Median days open
44 d
|
Median salary
$172k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Lattice Semiconductor | All employers we track in this specialty (411 roles · 61 employers) |
|---|---|---|
| Open roles in this specialty | 7 | 411 |
| Open roles in the wider Silicon Validation & Test family | 13 | 2227 · 113 employers |
| Median days open | 89 d | 44 d (+45 d vs this employer) |
| Median salary (USD postings) | — | $172k |
Skills observed across this category: silicon arrival, validation plans, product bring-up, SERDES, DDR, oscilloscopes
Who's hiring in this category
- AMD · 58 open roles · median 45 d
- Micron Technology · 39 open roles · median 41 d
- Qualcomm · 36 open roles · median 30 d
- NVIDIA · 26 open roles · median 25 d
- Microchip Technology · 22 open roles · median 70 d
- Graphcore · 20 open roles · median 123 d
How we counted: 411 open Post-Silicon Validation (Silicon Validation) roles from 61 employers tracked in the SemiconductorJobs index, counted 19 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.