Principal Engineer, Hardware Emulation - San Jose, California, United States
$219,000 - $351,000 USD yearly
Originally posted 19 October 2026 by the employer.
About the role
This role involves bringing up the hardware emulation platform for mixed-signal SoCs and developing monitors, checkers, and workflows for emulation environments. You will own and maintain chip-level emulation models to validate subsystems within networking chips and reproduce silicon failures on emulator hardware.
What you'll do
- Own and maintain emulation infrastructure and chip-level emulation models for validating subsystems within a networking chip. - Bring up the emulation platform for mixed-signal SoCs, and develop monitors and checkers for the environment. - Work with emulation vendors on hardware and tool issues, and enhance emulation methodology for robustness, test throughput, portability, and debuggability. - Debug emulation performance and area issues, runtime analysis of emulation results, and test-planning leveraging simulation-based design verification flows. - Collaborate cross-functionally with simulation, firmware, and software test teams to support pre-silicon chip validation, SW test bring-up, and failure reproduction from real silicon. - Work with hardware design teams to triage and fix design issues using hardware emulators.
What you'll need
- BS in Computer, Electrical, or Electronic Engineering or Computer Science with 20 years of relevant experience, or an MS with 18 years of relevant experience. - Technical proficiency and hands-on emulation experience on hardware emulator platforms: Palladium or Zebu. - Experience with emulation compile flows, wave dumps, triggers, waveform debug, and running tests. - Experience writing scripts in Perl or Python, and exposure to Makefile or other build flows. - Experience with waveform debug tools such as Verdi or SimVision. - Solid understanding of Verilog and SystemVerilog RTL design, with exposure to synthesizable SystemVerilog/Verilog code and SVAs.
Skills: hardware emulation, Palladium, Zebu, emulation compile flow, waveform debug, Verilog SystemVerilog RTL
This role has been open 0 days — well below the 66-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1201
|
Median days open
66 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Samsung Semiconductor | All employers we track in this specialty (1201 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 1201 |
| Open roles in the wider Digital Design & Verification family | 14 | 3224 · 116 employers |
| Median days open | 110 d | 66 d (+44 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: hardware emulation, Palladium, Zebu, emulation compile flow, waveform debug, Verilog SystemVerilog RTL
Who's hiring in this category
- Qualcomm · 110 open roles · median 40 d
- AMD · 95 open roles · median 52 d
- NVIDIA · 84 open roles · median 60 d
- Synopsys · 64 open roles · median 34 d
- SiFive · 55 open roles · median 76 d
- Cadence Design Systems · 50 open roles · median 118 d
How we counted: 1201 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 19 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.