Silicon Validation Engineer - Mountain View, CA, United States
$175,000 - $450,000 USD yearly
Originally posted 28 July 2026 by the employer.
MatX is developing full-stack solutions from silicon to systems to train and run ML workloads for AGI.
About the role
This role involves owning silicon validation from initial power-on through feature validation and production readiness. The work focuses on delivering performant and functionally accurate silicon for MatX products across compute, memory management, high-speed connectivity, and other key technologies.
What you'll do
- Own silicon bring-up and validation from first power-on through feature validation and production readiness.
- Develop and execute validation plans for chip-level and SiP-level functionality, performance, reliability, and system behavior.
- Debug complex failures using logs, registers, traces, waveforms, firmware output, and lab equipment.
- Analyze issues across RTL, firmware, software, board, package, and silicon boundaries.
- Collaborate with architecture, design, DV, emulation, firmware, software, and product engineering teams.
- Define observability and debug requirements and improve validation automation, execution, and failure triage.
What you'll need
- Strong hands-on experience in silicon validation, post-silicon bring-up, or hardware emulation.
- Experience validating complex SoCs, accelerators, or highly integrated silicon products.
- Strong understanding of digital hardware, SoC architecture, and hardware-firmware interaction.
- Proven ability to debug complex cross-functional failures and drive them to root cause.
- Experience working with real silicon and lab platforms.
- Familiarity with firmware, embedded software, drivers, and low-level hardware access.
- Ability to read and understand C or C++ code for debug purposes.
- Python or similar scripting experience.
- Ability to read specifications, register descriptions, validation plans, and relevant RTL.
Nice to have
- Experience with pre-silicon and post-silicon validation.
- Experience with Cadence Palladium.
- Experience with SystemVerilog, UVM, assertions, coverage, or waveform debug.
- Experience bringing up first silicon.
- Experience with HBM, DDR, PCIe, CXL, Ethernet, die-to-die interfaces, or advanced packaging.
- Familiarity with JTAG, oscilloscopes, logic analyzers, or protocol analyzers.
Skills: silicon bring-up, chip-level functionality, debug failures, hardware-firmware interactions, lab validation
This role has been open 82 days — well above the 43-day median for Post-Silicon Validation roles.
Post-Silicon Validation · Silicon Validation
|
Open roles in category
410
|
Median days open
43 d
|
Median salary
$172k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | MatX | All employers we track in this specialty (410 roles · 61 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 410 |
| Open roles in the wider Silicon Validation & Test family | 6 | 2219 · 113 employers |
| Median days open | 82 d | 43 d (+39 d vs this employer) |
| Median salary (USD postings) | — | $172k |
Skills observed across this category: silicon bring-up, chip-level functionality, debug failures, hardware-firmware interactions, lab validation
Who's hiring in this category
- AMD · 58 open roles · median 44 d
- Micron Technology · 39 open roles · median 40 d
- Qualcomm · 36 open roles · median 29 d
- NVIDIA · 26 open roles · median 24 d
- Microchip Technology · 22 open roles · median 69 d
- Graphcore · 20 open roles · median 122 d
How we counted: 410 open Post-Silicon Validation (Silicon Validation) roles from 61 employers tracked in the SemiconductorJobs index, counted 18 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.