Silicon Validation Engineer - CA, Santa Clara, United States
$116,000 - $218,500 USD yearly
Originally posted 10 September 2026 by the employer.
This role is at the rare intersection of architecture, silicon bring-up, and production within the HW ArchDev Methodology team.
About the role
This role involves designing validation strategies for complex architectures and driving silicon bring-up from early architecture definition through production.
What you'll do
- Design system-level validation strategies for complex architectures, corner cases, PVT, large-scale behavior, and feature interactions
- Build AI-assisted and data-driven validation workflows to improve coverage, debug turnaround, and efficiency
- Profile real workloads: training, inference, HPC, video, and emerging applications
- Deploy automation and telemetry pipelines that scale across products and teams
- Drive silicon bring-up and root-cause debug with reusable, high-leverage methods
What you'll need
- BS/MS in EE/CE (or equivalent experience)
- 2+ years in silicon bring-up, ASIC validation, or system-level debug
- Grounding in PVT, timing (STA), signal integrity, power, and high-speed IO (PCIe, chip-to-chip)
- Understanding of firmware/driver-hardware interaction
- Experience or curiosity around data-driven workflows, telemetry, and AI/LLM-assisted development
Skills: silicon bring-up, ASIC validation, system-level debug, validation strategies, AI accelerators
This role has been open 33 days — below the 41-day median for Post-Silicon Validation roles.
Post-Silicon Validation · Silicon Validation
|
Open roles in category
400
|
Median days open
41 d
|
Median salary
$174k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (400 roles · 62 employers) |
|---|---|---|
| Open roles in this specialty | 25 | 400 |
| Open roles in the wider Silicon Validation & Test family | 94 | 2223 · 112 employers |
| Median days open | 21 d | 41 d (−20 d vs this employer) |
| Median salary (USD postings) | — | $174k |
Skills observed across this category: silicon bring-up, ASIC validation, system-level debug, validation strategies, AI accelerators
Who's hiring in this category
- AMD · 57 open roles · median 41 d
- Micron Technology · 39 open roles · median 36 d
- Qualcomm · 36 open roles · median 28 d
- NVIDIA (this employer) · 25 open roles · median 21 d
- Graphcore · 21 open roles · median 119 d
- Microchip Technology · 19 open roles · median 69 d
How we counted: 400 open Post-Silicon Validation (Silicon Validation) roles from 62 employers tracked in the SemiconductorJobs index, counted 14 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.