Silicon Packaging Design Engineer - Arizona, Phoenix, United States
$105,650 - $149,150 USD yearly
Originally posted 26 April 2026 by the employer. Relisted by the employer on 22 August 2026.
About the role
As a Silicon Packaging Design Engineer, you will be responsible for the end-to-end development of substrate designs, from concept through tape-out, ensuring optimal performance, cost efficiency, and manufacturability.
What you'll do
- Drive the physical layout and routing of package designs, aligning with silicon, package, and board performance requirements. - Perform substrate fit and routing studies to evaluate design, performance, and cost tradeoffs. - Define and implement substrate design rules, conducting reviews to meet quality standards. - Analyze data, resolve Design Rule Checks (DRCs), and optimize package designs for manufacturability and performance. - Collaborate with cross-functional teams to optimize pinout and silicon-package-board interactions. - Deliver documentation and collateral into the product lifecycle management system of record.
What you'll need
- Bachelor's degree with 1+ years of experience, or Master's degree with 6+ months of experience in Electrical Engineering, Mechanical Engineering, or Material Sciences. - 6+ months of experience or familiarity with microelectronic package or PCB physical layout design and manufacturing processes. - Familiarity with package design tools such as Siemens Xpedition, Cadence Allegro Package Design, AutoCAD, or SolidWorks. - Familiarity with physical layout aspects of substrate design, including custom layouts, floor plans, or schematic layout conversion.
Nice to have
- Experience in microelectronic package substrate design, package I/O routing, and technology development. - Familiarity with microelectronic package electrical modeling and simulation tools such as PowerDC, HyperLynx, Q3D, and HFSS. - Experience with package design tools such as Package Layout Automation (PLA) and FIELD. - Experience with scripting using Python, VB, C, or similar languages.
Skills: package design, physical layout, routing, DRC, substrate design
This role has been open 211 days — well above the 61-day median for Packaging Engineering roles.
Packaging Engineering · Packaging
|
Open roles in category
208
|
Median days open
61 d
|
Median salary
$166k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Intel Corporation | All employers we track in this specialty (208 roles · 41 employers) |
|---|---|---|
| Open roles in this specialty | 9 | 208 |
| Open roles in the wider Process, Fab & Equipment family | 192 | 10037 · 107 employers |
| Median days open | 111 d | 61 d (+50 d vs this employer) |
| Median salary (USD postings) | — | $166k |
Skills observed across this category: package design, physical layout, routing, DRC, substrate design
Who's hiring in this category
- Renesas Electronics · 30 open roles · median 38 d
- Infineon Technologies · 25 open roles · median 42 d
- Micron Technology · 21 open roles · median 41 d
- onsemi · 16 open roles · median 31 d
- Monolithic Power Systems · 11 open roles · median 220 d
- Intel Corporation (this employer) · 9 open roles · median 111 d
How we counted: 208 open Packaging Engineering (Packaging) roles from 41 employers tracked in the SemiconductorJobs index, counted 26 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Process, Fab & Equipment family row. Figures refresh nightly.