Silicon Digital IP / Subsystem Architect - Bengaluru, Karnataka, India
Originally posted 22 September 2026 by the employer — open 0 days.
About the role
This role defines the architecture and technical direction of complex semiconductor IPs and subsystems at Astera Labs. The architect will own the architecture definition from requirements through implementation for technologies like CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based solutions.
What you'll do
- Define architecture for complex IP blocks and SoC subsystems based on product and system requirements.
- Translate system requirements into architecture, specifications, interfaces, and performance targets.
- Define microarchitecture, data paths, control paths, interfaces, clocking, reset, power, and error-handling mechanisms.
- Evaluate architectural trade-offs across performance, power, area, latency, bandwidth, scalability, and complexity.
- Define interfaces and protocols such as PCIe, UALink, AXI, APB, CHI, or other high-speed/interconnect protocols.
- Develop architecture specifications, block diagrams, interface specifications, and technical documentation.
What you'll need
- 20+ years of experience.
- Strong background in IP architecture and microarchitecture.
- Strong understanding of digital design, computer architecture, memory systems, interconnects, and SoC design.
- Experience with high-speed interfaces and/or coherent interconnects.
- Strong understanding of performance modeling, bandwidth, latency, and system-level trade-offs.
- Excellent technical communication and problem-solving skills.
Nice to have
- Experience with PCIe, UALink, CXL, Ethernet, CCIX, CHI, or similar technologies.
- Experience with AI/accelerator, networking, compute, or high-performance SoC architectures.
- Experience taking IP/subsystems from architecture through silicon production.
Skills: IP architecture, SoC subsystems, microarchitecture, performance modeling, high-speed interfaces, PCIe
This role has been open 0 days — well below the 67-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
448
|
Median days open
67 d
|
Median salary
$237k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (448 roles · 63 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 448 |
| Open roles in the wider Digital Design & Verification family | 54 | 3053 · 114 employers |
| Median days open | 79 d | 67 d (+12 d vs this employer) |
| Median salary (USD postings) | — | $237k |
Skills observed across this category: IP architecture, SoC subsystems, microarchitecture, performance modeling, high-speed interfaces, PCIe
Who's hiring in this category
- Qualcomm · 68 open roles · median 81 d
- NVIDIA · 60 open roles · median 46 d
- AMD · 35 open roles · median 74 d
- Arm Holdings · 27 open roles · median 89 d
- Renesas Electronics · 20 open roles · median 68 d
- NXP Semiconductors · 19 open roles · median 91 d
How we counted: 448 open SoC/Chip Architecture (SOC Architecture) roles from 63 employers tracked in the SemiconductorJobs index, counted 22 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.