Signal Integrity Architect, PCIe/CXL - Santa Clara, California, United States of America
$221,100 - $331,700 USD yearly
Originally posted 15 September 2026 by the employer.
Develop SI methodology and validation strategies for PCIe and CXL interfaces.
About the role
As a Signal Integrity Architect, you will provide technical and people leadership for data center server platforms. This role focuses on establishing SI methodology, validation strategy, design guidelines, and product-level signoff criteria across memory and SerDes interfaces, package-to-board integration, PCBs, cables, and system interconnects, with an emphasis on PCIe/CXL.
What you'll do
- Lead and develop the Signal Integrity team, including hiring, coaching, and performance management.
- Define signal integrity strategy, methodology, and best practices for data center products.
- Collaborate with SoC, packaging, and system design teams to develop system interconnect solutions.
- Review and validate die/package signal integrity solutions and approve their integration into server products.
- Establish design rules, signoff criteria, correlation plans, and validation processes for high-speed interfaces.
- Lead the development of SI models, simulation frameworks, and analysis flows across memory and high-speed serial interfaces.
What you'll need
- Master's degree in Electrical Engineering, Computer Engineering, or a related field.
- 10 years of experience in signal integrity analysis, simulation, and validation of high-speed digital systems.
- Experience managing a signal integrity engineering team.
- Strong knowledge of SI fundamentals, including transmission line theory, channel analysis, crosstalk, S-parameters, jitter analysis, and system-level performance optimization.
- Working knowledge of power integrity concepts, including PDN analysis and EMIR considerations.
- Expertise in DDR5/LPDDR6 interfaces and/or high-speed SerDes technologies such as PCIe, CXL, Ethernet, and UCIe.
- Proficiency with simulation tools such as ANSYS HFSS, Cadence Sigrity, Dassault Systèmes CST, Keysight ADS, and Synopsys HSPICE.
- Hands-on experience creating SI models and performing both frequency-domain and time-domain simulations.
- Proficiency in Unix/Linux environments and scripting for EDA tool automation.
- Strong understanding of packaging and PCB technologies, design methodologies, and manufacturing processes.
- Familiarity with advanced packaging technologies, including CoWoS, InFO, EMIB, RDL, and other 2.5D/3D integration approaches.
- Experience with electrical validation and compliance testing using oscilloscopes, VNAs, TDR systems, protocol analyzers, traffic generators, and related laboratory equipment.
Nice to have
- Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
- 15 years of experience in signal integrity analysis, simulation, validation, and architecture of high-speed systems.
- In-depth understanding of computational electromagnetics, signal integrity architecture, and transmission line theory.
- Expertise in DDR5 and LPDDR6 timing budgets, PHY design, link analysis, and margin characterization.
- Experience with PCIe Gen 6, CXL, Ethernet, UCIe, and 112Gbps serial communication channels.
- Experience with package and PCB design tools such as Cadence Allegro.
- Proficiency in MATLAB, Python, Perl, or comparable scripting and automation environments.
- Experience developing server, AI, HPC, data center, or rack-scale computing platforms.
Skills: Signal Integrity, high-speed digital systems, DDR5/LPDDR6, SerDes technologies, advanced packaging
This role has been open 28 days — well below the 81-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
241
|
Median days open
81 d
|
Median salary
$177k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (241 roles · 48 employers) |
|---|---|---|
| Open roles in this specialty | 18 | 241 |
| Open roles in the wider Analog & Mixed-Signal family | 70 | 1399 · 105 employers |
| Median days open | 59 d | 81 d (−22 d vs this employer) |
| Median salary (USD postings) | — | $177k |
Skills observed across this category: Signal Integrity, high-speed digital systems, DDR5/LPDDR6, SerDes technologies, advanced packaging
Who's hiring in this category
- Synopsys · 31 open roles · median 29 d
- AMD · 30 open roles · median 38 d
- Cadence Design Systems · 19 open roles · median 187 d
- Qualcomm (this employer) · 19 open roles · median 61 d
- Micron Technology · 13 open roles · median 74 d
- Apple · 12 open roles · median 15 d
How we counted: 241 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 48 employers tracked in the SemiconductorJobs index, counted 14 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.