Signal Integrity Engineer – Memory Interface - Austin, United States
Originally posted 16 September 2026 by the employer.
Work on memory interface signal integrity for Apple SoCs, covering package to board.
About the role
This role involves developing System-on-Chips (SoCs) for Apple's mobile devices, with specific responsibility for memory interface signal integrity from package to board. The position focuses on memory interfaces such as DDR and LPDDR.
What you'll do
- Work on electrical and physical design of memory systems.
- Perform electrical extraction and validation of package and MLB.
- Collaborate with circuit and controller teams to optimize memory system design.
- Conduct SI and PI modeling, simulation, and characterization of memory interfaces.
- Develop and execute test plans to validate signal and power integrity.
- Work with product engineering and system engineering to debug and improve product yield.
What you'll need
- BS + 10 years of industry experience.
- Prior design and modeling experience with DDR or LPDDR interfaces.
- Familiarity with signal and power integrity issues of memory interfaces.
- Experience with product package/board design and analysis, PI/SI methodology development, and lab correlation/validation.
- Strong fundamentals in 3D/2D EM simulation tools and transmission line theory.
- Proficient in Python with strong foundational coding skills.
Nice to have
- MSEE + 8 years of industry experience or Ph.D.
- Familiarity with lab equipment: VNA, TDR, real-time scope, spectrum analyzer.
- Expertise in leveraging generative AI coding assistants to enhance productivity.
Skills: signal and power integrity, memory interfaces, package/board design, EM simulation, VNA, TDR, real-time scope
This role has been open 27 days — well below the 81-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
241
|
Median days open
81 d
|
Median salary
$177k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Apple | All employers we track in this specialty (241 roles · 48 employers) |
|---|---|---|
| Open roles in this specialty | 12 | 241 |
| Open roles in the wider Analog & Mixed-Signal family | 35 | 1399 · 105 employers |
| Median days open | 15 d | 81 d (−66 d vs this employer) |
| Median salary (USD postings) | — | $177k |
Skills observed across this category: signal and power integrity, memory interfaces, package/board design, EM simulation, VNA, TDR, real-time scope
Who's hiring in this category
- Synopsys · 31 open roles · median 29 d
- AMD · 30 open roles · median 38 d
- Cadence Design Systems · 19 open roles · median 187 d
- Qualcomm · 19 open roles · median 61 d
- Micron Technology · 13 open roles · median 74 d
- Apple (this employer) · 12 open roles · median 15 d
How we counted: 241 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 48 employers tracked in the SemiconductorJobs index, counted 14 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.