SerDes Validation Leader - Remote
$180,000 - $260,000 USD yearly
Originally posted 14 September 2026 by the employer.
About the role
You will own the physical-layer implementation, configuration, tuning, and post-silicon validation of data links, including 112G and 224G PAM4. This hands-on role takes SerDes IP macros from integration through bring-up and tunes equalization parameters across cable, backplane, and board-level channels.
What you'll do
- Drive implementation and register-level configuration of high-speed SerDes IP blocks across custom hardware systems. - Own transceiver equalization tuning, including CTLE, FFE, and DFE tap optimization, to maximize eye margin and minimize bit error rates across cable, backplane, and board-level topologies. - Lead post-silicon physical-layer bring-up, characterization, and debugging of 112G and 224G PAM4 links. - Use high-bandwidth oscilloscopes, BERTs, pattern generators, and protocol analyzers to validate link performance and isolate issues. - Collaborate closely with SI/PI engineers to correlate lab-measured link behavior with layout, simulation, and channel models. - Work with firmware teams to support real-time link monitoring, configuration control, and automated validation flows. - Develop and run script-based lab automation, including Python-based test, measurement, and characterization workflows.
What you'll need
- Hands-on experience bringing up and validating physical 56G, 112G, or 224G PAM4 links, or high-speed PCIe Gen5/Gen6 interfaces. - Practical understanding of SerDes implementation, configuration, equalization, and physical-layer debug. - Knowledge of how TX/RX equalization settings affect signal integrity, jitter profiles, eye margin, and BER. - Proficiency with high-speed lab equipment, including BERTs, real-time or sampling oscilloscopes, pattern generators, and protocol analyzers. - Experience with automated, script-based testing and lab characterization, preferably using Python. - Ability to debug link issues across silicon, board, cable, backplane, firmware, and system-level interactions.
Nice to have
- Experience with 112G or 224G PAM4 links in data center, networking, switch, accelerator, or high-performance compute environments. - Familiarity with Ethernet, PCIe, CXL, or other high-speed protocols. - Experience working with SerDes IP from major commercial IP providers or custom in-house SerDes teams. - Exposure to channel modeling, compliance testing, and production validation flows.
Skills: SerDes, 112G PAM4, equalization tuning, post-silicon validation, high-speed lab equipment
This role has been open 43 days — well below the 71-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
247
|
Median days open
71 d
|
Median salary
$191k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Delos Data | All employers we track in this specialty (247 roles · 47 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 247 |
| Open roles in the wider Analog & Mixed-Signal family | 2 | 1495 · 107 employers |
| Median days open | 43 d | 71 d (−28 d vs this employer) |
| Median salary (USD postings) | — | $191k |
Skills observed across this category: SerDes, 112G PAM4, equalization tuning, post-silicon validation, high-speed lab equipment
Who's hiring in this category
- Synopsys · 34 open roles · median 36 d
- AMD · 27 open roles · median 45 d
- Cadence Design Systems · 21 open roles · median 140 d
- Qualcomm · 21 open roles · median 69 d
- Micron Technology · 13 open roles · median 41 d
- Apple · 12 open roles · median 25 d
How we counted: 247 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 47 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.
Delos Data
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