Senior Verification Engineer - Hardware - CA, Santa Clara, United States
$168,000 - $310,500 USD yearly
Originally posted 12 June 2026 by the employer.
About the role
NVIDIA is looking for a Senior Verification Engineer to join the Emulation division onsite in Santa Clara, CA.
What you'll do
- Bring up SOCs on emulation, root causing SoC/Processor test fails and emulator environment issues. - Collaborate with Design, DV, Power, Silicon Validation, Performance, and Software teams. - Work with emulation vendors to debug issues using various tools.
What you'll need
- M.S or equivalent experience in Electrical Engineering, Computer Science, Computer Engineering, or a related field. - 3+ years of experience. - Proficiency in Verilog and/or VHDL, C/C++, and SystemVerilog. - Experience with UVM verification environments and scripting with Perl, Python, and C/C++. - Familiarity with hierarchical design approaches, top-down design, SoC, and system level verification. - Ability to work on-site at the Santa Clara, CA office.
Skills: emulation environments, UVM verification, SystemVerilog, SOC verification, C/C++ DPI Transactors
This role has been open 132 days — well above the 65-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1241
|
Median days open
65 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (1241 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 84 | 1241 |
| Open roles in the wider Digital Design & Verification family | 225 | 3322 · 115 employers |
| Median days open | 65 d | 65 d (same as this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: emulation environments, UVM verification, SystemVerilog, SOC verification, C/C++ DPI Transactors
Who's hiring in this category
- Qualcomm · 115 open roles · median 42 d
- AMD · 94 open roles · median 52 d
- NVIDIA (this employer) · 85 open roles · median 64 d
- Synopsys · 66 open roles · median 38 d
- SiFive · 55 open roles · median 80 d
- Cadence Design Systems · 52 open roles · median 122 d
How we counted: 1241 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 23 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.