Senior Technical Staff Engineer - Analog Design (SRAM Design) - CA - San Jose - 3850 N. First St, United States
$91,000 - $232,000 USD yearly
Originally posted 3 June 2026 by the employer.
About the role
This role is responsible for the design of complex, multiport SRAM blocks with programmable features and modes for use in advanced and low-power FPGA devices. You will work alongside circuit design engineers and collaborate with architecture, ASIC, firmware, verification, and test teams.
What you'll do
- Define, estimate, develop, and optimize full custom high-speed SRAM blocks for speed, low power, area, and feature set. - Define internal memory array architecture for redundancy, ECC compliance, and optimal speed with lowest power. - Simulate and evaluate SRAM cells for cell stability, write and read margin, minimum cell operating and state retention supply levels, and noise margin. - Develop and optimize sense amps for reliable operation, high speed, low power, and sufficient noise margin. - Run experiments using memory compilers from EDA vendors for embedded memories to evaluate PPA trade-offs. - Create and verify circuit schematics, build functional Verilog models, and drive silicon validation of SRAM blocks for functionality and performance.
What you'll need
- Bachelor's degree in Computer Engineering, Electrical Engineering, or Computer Science. - 12+ years of experience in custom SRAM design and/or memory circuit design. - High degree of SPICE simulation proficiency. - Experience with full custom design EDA tools, scripting, managing simulation queues, and data capture and analysis. - Demonstrated ability to develop and test Verilog simulation models and compare back to SPICE-based models. - Experience simulating and analyzing yield impact, reliability, and power.
Nice to have
- Master's degree in Computer Engineering, Electrical Engineering, or Computer Science. - Experience in analog and full custom design, as well as FPGA or ASIC development. - Experience in functional verification and timing characterization. - Experience in low power design including dual rail, array biasing, dynamic low power mode switching (sleep, power gating, column array muxing). - Experience in OCV timing and yield variation analyses using Solido and Monte Carlo.
Skills: SRAM, memory array architecture, SPICE simulation, memory cell, sense amps
This role has been open 123 days — well above the 68-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
310
|
Median days open
68 d
|
Median salary
$200k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Microchip Technology | All employers we track in this specialty (310 roles · 31 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 310 |
| Median days open | 123 d | 68 d (+55 d vs this employer) |
| Median salary (USD postings) | — | $200k |
Skills observed across this category: SRAM, memory array architecture, SPICE simulation, memory cell, sense amps
Who's hiring in this category
- Micron Technology · 158 open roles · median 88 d
- Synopsys · 32 open roles · median 64 d
- Qualcomm · 19 open roles · median 85 d
- SanDisk · 17 open roles · median 51 d
- Broadcom · 16 open roles · median 65 d
- NVIDIA · 8 open roles · median 46 d
How we counted: 310 open Memory Design (Memory Design) roles from 31 employers tracked in the SemiconductorJobs index, counted 24 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.