Senior Static Timing Analysis (STA) Engineer - United States
$164,470 - $269,100 USD yearly
Originally posted 2 September 2026 by the employer.
This role focuses on delivering high-performance, power-efficient System-on-Chip (SoC) designs.
About the role
This role involves driving the development of semiconductor products by performing static timing analysis and optimization. You will ensure successful timing convergence, signal integrity, and performance optimization for complex System-on-Chip (SoC) designs.
What you'll do
- Perform SOC level timing analysis and optimization to meet functional and performance requirements.
- Generate and verify timing constraints, addressing violations at chip or block level for SoCs.
- Conduct timing rollups and develop optimized clock networks for functionality, performance, and power efficiency.
- Define methodologies to produce high-quality timing models and enable efficient physical design execution.
- Establish process, voltage, and temperature (PVT) conditions for timing analysis, aligning with product plans and binning strategies.
- Contribute to the development of tools, flows, and methodologies that enhance SoC physical design and timing processes.
What you'll need
- Bachelor's degree in Computer Engineering, Computer Science, or related STEM discipline and 6+ years of industry experience; OR a Master's degree in the same fields and 4+ years of experience.
- 5+ years of experience with SOC level static timing analysis, clock network design, and timing closure methodologies.
- 5+ years of experience with timing constraint adaptation, physical design knowledge, and optimization techniques.
- 5+ years of experience with industry-standard tools for timing analysis, extraction, and physical design.
- 5+ years of experience with TCL scripting and timing budgeting processes.
Nice to have
- PhD in Computer Engineering, Computer Science, or related STEM discipline and 2+ years of experience.
- Knowledge of tools, flows, and methodologies for high-performance physical design.
- Experience with SoC clocking methodologies.
- DFT architecture knowledge.
Skills: static timing analysis, timing convergence, timing constraints, clock networks, physical design
This role has been open 46 days — well below the 60-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
659
|
Median days open
60 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Intel Corporation | All employers we track in this specialty (659 roles · 80 employers) |
|---|---|---|
| Open roles in this specialty | 36 | 659 |
| Open roles in the wider Physical Implementation family | 60 | 1440 · 110 employers |
| Median days open | 11 d | 60 d (−49 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: static timing analysis, timing convergence, timing constraints, clock networks, physical design
Who's hiring in this category
- Qualcomm · 119 open roles · median 45 d
- AMD · 63 open roles · median 24 d
- NVIDIA · 37 open roles · median 72 d
- Synopsys · 37 open roles · median 32 d
- Intel Corporation (this employer) · 36 open roles · median 11 d
- Broadcom · 30 open roles · median 97 d
How we counted: 659 open Physical Design (Physical Design) roles from 80 employers tracked in the SemiconductorJobs index, counted 18 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.