Senior Staff Test Engineer - Technology & Solutions - San Jose
$147,400 - $202,700 USD yearly
Originally posted 21 July 2026 by the employer.
Lead 93K test program development and mixed-signal validation for 100BASE-T1 and 1000BASE-T1 Automotive Ethernet ICs.
About the role
As a Senior Staff Test Engineer in the Research & Development team, you will own end-to-end test program development and execution for automotive products. The focus covers Automotive Ethernet PHY/Switch ICs and Sensor bridge devices across 100BASE-T1 and 1000BASE-T1 standards on the Advantest V93000 platform.
What you'll do
- Own end-to-end 93K test program development for Automotive Ethernet PHY/Switch ICs and Sensor bridge devices (100BASE-T1, 1000BASE-T1). - Define test strategy, test plans, guard banding, and production release criteria aligned to automotive quality requirements. - Lead silicon bring-up, bench-to-ATE correlation, PLL/clock characterization, and PVT margin analysis. - Implement DFT-based test including scan, at-speed scan, MBIST/LBIST, JTAG, and ATPG pattern execution. - Drive yield improvement, false-fail reduction, test time optimization, and CP/FT correlation. - Support QUAL/ATEQ readiness, automotive quality documentation, production change control, and customer RMA root cause investigations.
What you'll need
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline. - 7+ years of semiconductor test engineering experience on Advantest V93000 (93K) in a production environment. - Demonstrated Automotive NPI ownership from test concept through HVM release. - Hands-on mixed-signal/PHY test experience, including PLL/clock validation, analog parametric characterization, and Tx/Rx path testing. - Experience with DFT execution encompassing scan, MBIST, JTAG, and ATPG. - Familiarity with CP/FT flows, manufacturing ramp, OSAT collaboration, and automotive standards including AEC-Q100, IATF 16949, PPAP, and FMEA.
Nice to have
- Scripting and data skills with Python, C/C++, JMP, or SQL. - Knowledge of ISO26262 functional safety requirements.
This role has been open 90 days — well above the 31-day median for Silicon Test Engineering roles.
Silicon Test Engineering · DFT Test
|
Open roles in category
550
|
Median days open
31 d
|
Median salary
$173k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Infineon Technologies | All employers we track in this specialty (550 roles · 78 employers) |
|---|---|---|
| Open roles in this specialty | 42 | 550 |
| Open roles in the wider Silicon Validation & Test family | 110 | 2227 · 113 employers |
| Median days open | 40 d | 31 d (+9 d vs this employer) |
| Median salary (USD postings) | — | $173k |
Who's hiring in this category
- Teradyne · 75 open roles · median 25 d
- Renesas Electronics · 43 open roles · median 25 d
- Infineon Technologies (this employer) · 41 open roles · median 41 d
- Micron Technology · 29 open roles · median 35 d
- Qualcomm · 28 open roles · median 31 d
- Texas Instruments · 23 open roles · median 26 d
How we counted: 550 open Silicon Test Engineering (DFT Test) roles from 78 employers tracked in the SemiconductorJobs index, counted 19 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.