Senior / Staff SoC DRAM System Engineer - Hsinchu City, Taiwan
Originally posted 14 July 2026 by the employer.
This role focuses on DRAM system solutions for Qualcomm IE-IOT SoC platforms.
About the role
This role involves designing and developing DRAM system software solutions for Qualcomm IE-IOT SoC platforms, enabling high-performance, low-power, and real-time DRAM system experiences. Your work will support applications in surveillance, smart devices, retail systems, robotics, and edge AI.
What you'll do
- Design, develop, and evaluate DRAM system solutions for Qualcomm IE-IOT SoC platforms, including DRAM controller, PHY, timing, calibration, and memory subsystem integration.
- Lead DRAM bring-up, initialization, tuning, and validation on new SoC and hardware platforms.
- Configure and optimize memory controller and PHY settings to meet JEDEC requirements, power targets, bandwidth goals, latency constraints, and system-level performance objectives.
- Collaborate with cross-functional teams to integrate and debug memory subsystem behavior on Qualcomm IE-IOT SoC-based systems.
- Perform DRAM characterization, stress testing, margin analysis, retention testing, and signal/power integrity correlation.
- Analyze and resolve system-level memory issues across boot-up, suspend/resume, low-power modes, and runtime workloads.
What you'll need
- Master's degree in Electrical Engineering or a related field with 3 years of relevant experience, or a PhD in a related field.
- Strong understanding of LPDDR3/LPDDR4/LPDDR5 specifications, timing parameters, and calibration schemes.
- Experience in configuring DRAM registers and bring-up on embedded platforms.
- Familiarity with memory controller architecture and PHY interface tuning.
- Skilled in using logic analyzers, oscilloscopes, and memory test equipment.
- Comfortable with Linux-based embedded systems and debugging low-level software interactions with DRAM.
Nice to have
- Experience debugging kernel panics or stability issues caused by DRAM misconfiguration.
- Familiarity with memory low-power states, self-refresh, and power-saving strategies.
- Knowledge of post-silicon validation, including test pattern development and validation coverage planning.
- Experience working with DRAM vendors to understand datasheets, tuning recommendations, and errata.
Skills: DRAM system solutions, DRAM controller, PHY, LPDDR3/LPDDR4/LPDDR5, memory subsystem integration, DRAM characterization
This role has been open 82 days — well above the 69-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
287
|
Median days open
69 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (287 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 12 | 287 |
| Median days open | 150 d | 69 d (+81 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: DRAM system solutions, DRAM controller, PHY, LPDDR3/LPDDR4/LPDDR5, memory subsystem integration, DRAM characterization
Who's hiring in this category
- Micron Technology · 151 open roles · median 86 d
- Synopsys · 27 open roles · median 49 d
- SanDisk · 17 open roles · median 32 d
- Broadcom · 16 open roles · median 50 d
- Qualcomm (this employer) · 12 open roles · median 149 d
- NVIDIA · 7 open roles · median 59 d
How we counted: 287 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.