Senior/Staff NAND Process Integration Design Rule Engineer - Hyderabad - Phoenix Aquila, India
Originally posted 25 September 2026 by the employer.
About the role
This role involves defining physical design rules for current and future Non-Volatile Memory (NVM) technologies.
What you'll do
- Define physical design rules for current and future Non-Volatile Memory (NVM) technologies from conception to full production ramp.
- Interact with design teams to evaluate the feasibility of different layout and architecture options.
- Develop automated solutions and agentic capabilities for design rule coverage, accuracy, and consistency.
- Support design rule checking (DRC) of both base and mask layers.
- Define algorithms for generation of mask data from drawn base layer data.
- Involve projects across multi-disciplinary teams focusing on layout and mask generation issues.
What you'll need
- Master’s or PhD degree with at least 3 years of experience in the semiconductor industry in Process Integration, Yield Enhancement, Product Engineering, Test Structure Development, or Unit Process Development.
- Strong semiconductor device physics and VLSI silicon processing and integration flow knowledge.
- Proven ability to develop code and agentic solutions using Python or other industry standard programming languages.
- Exposure to design, design rule, and layout.
- Experience with CAD tools like Cadence Virtuoso, K2view, and Mentor Graphics DRV/RVE.
- Strong knowledge of advanced semiconductor process flow, scaling issues of memory (non-volatile/volatile memory technologies), and the function of major NAND components (BL sensing, Word-line driver, CMOS under array).
Skills: NAND, Design Rule, NVM technologies, layout, DRC, Cadence Virtuoso
This role has been open 32 days — well below the 71-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
309
|
Median days open
71 d
|
Median salary
$200k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (309 roles · 31 employers) |
|---|---|---|
| Open roles in this specialty | 157 | 309 |
| Median days open | 91 d | 71 d (+20 d vs this employer) |
| Median salary (USD postings) | — | $200k |
Skills observed across this category: NAND, Design Rule, NVM technologies, layout, DRC, Cadence Virtuoso
Who's hiring in this category
- Micron Technology (this employer) · 157 open roles · median 91 d
- Synopsys · 30 open roles · median 67 d
- Qualcomm · 19 open roles · median 88 d
- Broadcom · 17 open roles · median 68 d
- SanDisk · 17 open roles · median 54 d
- NVIDIA · 7 open roles · median 34 d
How we counted: 309 open Memory Design (Memory Design) roles from 31 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.