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d-Matrix

Senior Staff Hardware Qualification Engineer - Santa Clara, United States

d-Matrix Remote friendly (Santa Clara, United States) Full-time 6 months ago
Product Engineering & Quality

Originally posted 6 May 2026 by the employer.

About the role

As a Senior Staff Hardware Qualification Engineer, you will define and execute qualification strategies ensuring AI compute hardware—from ASIC substrates to rack-scale systems—withstands 24/7 data center environments.

What you'll do

- Define and execute comprehensive HW qualification plans across EVT, DVT, and PVT for AI accelerator systems, including PCIe cards, OAM modules, and chassis systems. - Lead HALT/HASS, thermal cycling, humidity, and vibration stress testing to identify marginalities in high-power ASIC designs. - Provide technical oversight for the validation of high-speed SerDes (112G/224G/PCIe), LPDDR, CoWoS designs, and complex PDN transients. - Drive root-cause failure analysis for complex system-level failures using X-ray, CT scan, and SEM/EDX. - Oversee the qualification of high-bandwidth interconnects and PCIe Gen5/6 link stability. - Partner with CMs and JDMs to align on test methodologies and production outgoing quality limits (OQL).

What you'll need

- BS or MS in Electrical Engineering, Mechanical Engineering, or Reliability Engineering. - 12+ years of experience in hardware qualification or reliability, specifically with high-performance computing (HPC), servers, or networking hardware. - Mastery of JEDEC, IPC, and Telcordia standards for hardware reliability. - Expert-level experience with high-speed oscilloscopes, logic analyzers, and environmental chambers. - Strong command of statistical methods including Weibull analysis, DOE, and JMP/Minitab to predict product life cycles and failure rates.

Nice to have

- Experience qualifying air and liquid cooling components (CDUs, cold plates, leak detection) for high-TDP AI systems. - Background in ASIC/package-level reliability, including electromigration and thermal stress analysis. - Familiarity with Python or LabVIEW for automating complex test sequences.

Skills: HW qualification, stress testing, HALT/HASS, failure analysis, JEDEC, environmental chambers

Market context

This role has been open 129 days — well above the 53-day median for Reliability Engineering roles.

Reliability Engineering · Reliability Engineering

Open roles in category
459
Median days open
53 d
Median salary
$154k
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
How d-Matrix compares in Reliability Engineering hiring
Metric d-Matrix All employers we track in this specialty (459 roles · 71 employers)
Open roles in this specialty 2 459
Open roles in the wider Process, Fab & Equipment family 2 10080 · 106 employers
Median days open 67 d 53 d (+14 d vs this employer)
Median salary (USD postings) — $154k

Skills observed across this category: HW qualification, stress testing, HALT/HASS, failure analysis, JEDEC, environmental chambers

Who's hiring in this category

  • Micron Technology · 82 open roles · median 127 d
  • Infineon Technologies · 32 open roles · median 46 d
  • Renesas Electronics · 27 open roles · median 39 d
  • Applied Materials · 19 open roles · median 53 d
  • STMicroelectronics · 19 open roles · median 29 d
  • Analog Devices · 18 open roles · median 63 d

How we counted: 459 open Reliability Engineering (Reliability Engineering) roles from 71 employers tracked in the SemiconductorJobs index, counted 23 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Process, Fab & Equipment family row. Figures refresh nightly.

Apply now
Santa Clara, United States
Hybrid
Full-time
6 months ago

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