Senior Staff Engineer, Custom IC Layout
Originally posted 4 October 2026 by the employer.
Drive Custom Compiler technical engagement and analog IP migration methodologies.
About the role
This role involves leading technical engagement for Custom IC Layout tools and methodologies with key customers in Korea, focusing on Custom Compiler and analog IP migration.
What you'll do
- Own Custom Compiler technical engagement at leading Korean foundry, memory, and fabless customers, driving tool deployment and methodology adoption.
- Lead on-site debug and root-cause analysis for blocker issues, working with customer layout teams and R&D to deliver solutions.
- Develop and validate node-to-node and fab-to-fab analog IP migration methodologies, building production-ready flows.
- Drive adoption of layout synthesis using ASO.ai and other Synopsys.ai solutions, integrating them into customer workflows.
- Build and deliver methodology decks, application notes, training materials, and customer-facing workshops.
- Validate new Custom Compiler features on customer reference designs at advanced nodes, providing feedback to R&D.
What you'll need
- BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field.
- 7+ years of hands-on experience in custom IC layout for analog, mixed-signal, memory, standard cell, or IP blocks, or in EDA Product Engineering or Application Engineering supporting custom layout tools.
- Proficiency with Synopsys Custom Compiler or Cadence Virtuoso, including layout editors, design rule checking, LVS flows, and parasitic extraction.
- Strong understanding of advanced-node design rules, physical verification flows, and parasitic-aware layout techniques.
- Scripting capability in SKILL, Python, or Tcl, with comfort working in Linux/Unix environments.
- Fluency in Korean and strong English communication skills, with the ability to present technical content and lead workshops.
Skills: Custom Compiler, custom IC layout, analog IP migration, layout synthesis, DRC/LVS, SKILL scripting
This role has been open 0 days — well below the 84-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
692
|
Median days open
84 d
|
Median salary
$193k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (692 roles · 76 employers) |
|---|---|---|
| Open roles in this specialty | 54 | 692 |
| Open roles in the wider Physical Implementation family | 87 | 1430 · 108 employers |
| Median days open | 35 d | 84 d (−49 d vs this employer) |
| Median salary (USD postings) | — | $193k |
Skills observed across this category: Custom Compiler, custom IC layout, analog IP migration, layout synthesis, DRC/LVS, SKILL scripting
Who's hiring in this category
- Cadence Design Systems · 165 open roles · median 167 d
- Synopsys (this employer) · 52 open roles · median 35 d
- NVIDIA · 41 open roles · median 73 d
- Micron Technology · 40 open roles · median 114 d
- Qualcomm · 37 open roles · median 74 d
- GlobalFoundries · 28 open roles · median 51 d
How we counted: 692 open EDA/CAD Engineering (EDA Tools) roles from 76 employers tracked in the SemiconductorJobs index, counted 6 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.