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Astera Labs

Senior/Staff Electronics Engineer - Board Validation - San Jose, California, United States

Astera Labs San Jose, California, United States 2 months ago
Digital Design & SoC Architecture

$133,200 - $185,000 USD yearly

Originally posted 4 August 2026 by the employer — open 44 days.

About the role

This role involves hardware electrical validation of PCBAs and related hardware products, linking hardware electrical design teams with post-silicon electrical validation teams. This position focuses on connectivity solutions utilizing CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor technologies.

What you'll do

  • Support Hardware Electrical Design teams from project kick-off to gerber out.
  • Develop comprehensive hardware electrical validation plans using correct test methods and processes.
  • Bring up PCBAs in the lab and execute electrical validation plans to validate all circuits.
  • Debug complex multi-point failures in hardware, including power regulators, DPMs, clock synthesizers, digital control paths, I2C, and SPI.
  • Rework components on PCBAs to unblock debugging activities.
  • Specify test equipment, develop test fixtures, and improve hardware lab functions.

What you'll need

  • Strong skills in electronic circuit analysis, testing, and debug.
  • Bachelor degree in EE with 3+ years of experience in hardware test or design.
  • Expert understanding of design and test for power regulators, PDNs, Bode, and clock generators.
  • Ability to produce test descriptions from schematic designs, execute, and document results.
  • Knowledge of the full hardware product lifecycle from Project Kick-off to RTM.
  • Experience with lab equipment for hardware test, such as oscilloscopes, e-loads, VNA, TDR, and environmental chambers.
  • Ability to automate lab equipment to optimize test processes, with Python preferred.

Nice to have

  • Measurements of high-speed interfaces like PCIe, DDR, and 25/50G/100G SERDES.
  • EMI/EMC compliance experience.
  • Technical writing skills, including ECOs, Bug Reports, Rework WIs, and MCOs.
  • Experience with PLM, Arena or equivalent.
  • Understanding of the ASIC/silicon product development process.
Market context

This role has been open 41 days — well below the 62-day median for Digital/RTL Design roles.

Digital/RTL Design · RTL Design

Open roles in category
921
Median days open
62 d
Median salary
$183k
See the full market breakdown ▾Category comparison, and who else is hiring
How Astera Labs compares in Digital/RTL Design hiring
Metric Astera Labs All employers we track in this specialty (921 roles · 101 employers)
Open roles in this specialty 24 921
Open roles in the wider Digital Design & Verification family 52 3009 · 114 employers
Median days open 39 d 62 d (−23 d vs this employer)
Median salary (USD postings) — $183k

Who's hiring in this category

  • Qualcomm · 134 open roles · median 58 d
  • AMD · 60 open roles · median 67 d
  • Synopsys · 56 open roles · median 31 d
  • NXP Semiconductors · 53 open roles · median 64 d
  • NVIDIA · 49 open roles · median 50 d
  • Analog Devices · 38 open roles · median 75 d

How we counted: 921 open Digital/RTL Design (RTL Design) roles from 101 employers tracked in the SemiconductorJobs index, counted 17 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.

Apply now
San Jose, California, United States
On-site
$133,200 - $185,000 USD yearly
2 months ago

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