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Astera Labs

Senior/Staff Electronics Engineer - Board Validation - San Jose, California, United States

Astera Labs San Jose, California, United States 2 months ago
Digital Design & SoC Architecture

$133,200 - $185,000 USD yearly

Originally posted 4 August 2026 by the employer.

About the role

This role is for a Senior/Staff Electronics Engineer within the Hardware Electrical Validation team, focused on the electrical validation of PCBAs and related hardware products.

What you'll do

  • Support Hardware Electrical Design teams in de-risking circuits and modules from project kick-off to gerber out.
  • Develop comprehensive hardware electrical validation plans using correct test methods and processes.
  • Bring up PCBAs and execute electrical validation plans to validate all circuits on the board.
  • Debug complex multi-point hardware failures in power regulators, DPMs, clock synthesizers, digital control paths, I2C, and SPI.
  • Rework components on PCBAs to unblock debugging activities.
  • Pre-empt and de-risk system validation architectures by collaborating with System Validation teams.

What you'll need

  • Strong skills in electronic circuit analysis, comprehensive testing, and debug.
  • Bachelor's degree in EE with 3+ years of experience in hardware test or design.
  • Expert understanding of design and test for power regulators, PDNs, Bode, and clock generators.
  • Ability to produce test descriptions from schematic designs, execute, and document results.
  • Demonstrated knowledge of the full hardware product lifecycle from Project Kick-off to RTM.
  • Experience with lab equipment for hardware test including oscilloscopes, e-loads, VNA, TDR, and environmental chambers.
  • Ability to automate lab equipment to optimize test processes, with Python preferred.

Nice to have

  • Experience with measurements of high-speed interfaces like PCIe, DDR, and 25/50G/100G SERDES.
  • Knowledge of EMI/EMC compliance.
  • Technical writing skills for ECOs, Bug Reports, Rework WIs, and MCOs.
  • Experience with PLM, Arena, or equivalent.
  • Understanding of the ASIC/silicon product development process.
Market context

This role has been open 53 days — below the 62-day median for Digital/RTL Design roles.

Digital/RTL Design · RTL Design

Open roles in category
986
Median days open
62 d
Median salary
$185k
See the full market breakdown ▾Category comparison, and who else is hiring
How Astera Labs compares in Digital/RTL Design hiring
Metric Astera Labs All employers we track in this specialty (986 roles · 101 employers)
Open roles in this specialty 25 986
Open roles in the wider Digital Design & Verification family 58 3109 · 115 employers
Median days open 19 d 62 d (−43 d vs this employer)
Median salary (USD postings) — $185k

Who's hiring in this category

  • Qualcomm · 141 open roles · median 62 d
  • AMD · 68 open roles · median 65 d
  • Synopsys · 65 open roles · median 24 d
  • NXP Semiconductors · 54 open roles · median 72 d
  • NVIDIA · 47 open roles · median 53 d
  • Analog Devices · 46 open roles · median 37 d

How we counted: 986 open Digital/RTL Design (RTL Design) roles from 101 employers tracked in the SemiconductorJobs index, counted 29 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.

Apply now
San Jose, California, United States
On-site
$133,200 - $185,000 USD yearly
2 months ago

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