Senior Staff Design Verification Engineer
Verification strategy and execution for memory data buffer products, including DDR6.
Originally posted 10 November 2026 by the employer.
About the role
Provide technical leadership for the verification of memory interface products for data center, AI, and cloud computing applications. The role drives verification strategy and execution for memory data buffer products, including DDR6 and future generations.
What you'll do
- Define and drive verification strategies, methodologies, test plans, and coverage approaches for complex designs at the block and system level.
- Lead the development and optimization of SystemVerilog and UVM verification environments and testbenches.
- Drive verification execution, functional coverage, debugging, and coverage closure.
- Make independent technical decisions regarding verification methods, techniques, and priorities while analyzing complex issues and identifying root causes.
- Participate in architecture, feasibility, design, and technical reviews, serving as a subject matter expert in design verification.
- Mentor and provide technical guidance to verification engineers across projects and experience levels.
What you'll need
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent experience.
- 10+ years of related experience in semiconductor design verification, including technical leadership of complex verification efforts.
- Advanced proficiency with SystemVerilog and extensive hands-on experience with UVM (Universal Verification Methodology).
- Proven experience defining verification strategies and developing verification plans from product and design specifications.
- Deep experience developing, optimizing, and debugging UVM-based verification environments and testbenches.
- Strong experience with functional verification, coverage, checkers, test development, debugging, and coverage closure.
Nice to have
- Experience with DDR4, DDR5, memory interfaces, data buffers, or other high-speed memory technologies.
- Experience leading verification efforts across multiple blocks, features, or engineering groups.
- Experience developing verification methodologies or best practices with applicability beyond an individual project.
Skills: SystemVerilog, UVM, functional coverage, testbenches, coverage closure
More semiconductor jobs: Renesas Electronics jobs · Verification engineer jobs
First seen in our index 3 days ago, well below the 59-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1412
|
Median days since first seen
59 d
|
Category median salary (all employers)
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Renesas Electronics | All employers we track in this specialty (1412 roles · 101 employers) |
|---|---|---|
| Open roles in this specialty | 47 | 1412 |
| Open roles in the wider Digital Design & Verification family | 96 | 3617 · 122 employers |
| Median days since first seen | 22 d | 59 d (+37 d vs this employer) |
| Median salary (USD postings) | n/a | $185k |
Skills observed across this category: SystemVerilog, UVM, functional coverage, testbenches, coverage closure
Who's hiring in this category
- Qualcomm · 138 open roles · median 52 d
- NVIDIA · 109 open roles · median 74 d
- Apple · 107 open roles · median 17 d
- Synopsys · 90 open roles · median 53 d
- AMD · 81 open roles · median 65 d
- SiFive · 57 open roles · median 72 d
How we counted: 1412 open Design Verification (Design Verification) roles from 101 employers tracked in the SemiconductorJobs index, counted 14 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Digital Design & Verification family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.