Senior /Staff AMS Layout engineer-DPG-LPDDR - Hyderabad - Phoenix Aquila, India
Originally posted 22 July 2026 by the employer.
This role focuses on custom analog and mixed-signal layout for critical LPDDR PHY blocks.
About the role
This role involves owning and driving custom analog and mixed-signal layout for critical LPDDR PHY blocks, ensuring robust operation across PVT, low noise coupling, and high matching accuracy.
What you'll do
- Own and drive custom analog and mixed-signal layout for critical LPDDR PHY blocks.
- Lead high-speed LPDDR interface layout execution, addressing signal integrity challenges like skew control, impedance matching, shielding, crosstalk mitigation, and jitter sensitivity.
- Architect and implement scalable array-based layout strategies for DQ/DQS byte lanes, CA lanes, and replica paths.
- Drive integration of custom digital and mixed-signal blocks within the PHY, ensuring optimal clocking, congestion management, and isolation.
- Lead layout-aware co-design with circuit teams, enabling early closure of timing, noise, IR, EM, and parasitic effects.
- Own physical verification and signoff closure, including DRC/LVS, parasitic extraction, and simulation correlation.
What you'll need
- 3-12 years of hands-on experience in custom analog and high-speed layout design.
- Expertise in implementing critical analog blocks and LPDDR/high-speed interfaces at advanced technology nodes.
- Experience solving signal integrity challenges such as skew control, impedance matching, shielding, crosstalk mitigation, and jitter sensitivity.
- Ability to architect and implement scalable array-based layout strategies.
- Experience with physical verification and signoff closure, including DRC/LVS, parasitic extraction, and simulation correlation.
- Scripting experience (SKILL/Python/TCL) to improve productivity.
Skills: custom analog layout, LPDDR PHY, signal integrity, physical verification, DRC/LVS, PVT
This role has been open 81 days — well above the 69-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
287
|
Median days open
69 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (287 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 153 | 287 |
| Median days open | 86 d | 69 d (+17 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: custom analog layout, LPDDR PHY, signal integrity, physical verification, DRC/LVS, PVT
Who's hiring in this category
- Micron Technology (this employer) · 151 open roles · median 86 d
- Synopsys · 27 open roles · median 49 d
- SanDisk · 17 open roles · median 32 d
- Broadcom · 16 open roles · median 50 d
- Qualcomm · 12 open roles · median 149 d
- NVIDIA · 7 open roles · median 59 d
How we counted: 287 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.