Senior Speed Characterization Engineer - Silicon Co-Design Group - CA, Santa Clara, United States
$136,000 - $264,500 USD yearly
Originally posted 27 July 2026 by the employer.
This role focuses on silicon speed characterization from first power-on through production sign-off.
About the role
This role involves owning silicon speed characterization from first power-on through production sign-off, covering frequency, Vmin, Vmax, and timing margins across the full PVT space. The work includes defining what silicon can become, rather than just reporting what it does.
What you'll do
- Own silicon speed characterization from first power-on through production sign-off, covering frequency, Vmin, Vmax, and timing margins across the full PVT space.
- Close the correlation gap between pre-silicon timing analysis and measured silicon, producing actionable analysis.
- Trace failures to their source, whether microarchitectural bottleneck, critical path, clocking issue, or process corner, and drive resolution.
- Own and build AI agents for automated test orchestration, intelligent data pipelines, and analysis flows.
- Sit at the decision table, providing data to surface tradeoffs across architecture, VLSI, ASIC, firmware, and product teams.
What you'll need
- BS or MS in Electrical Engineering, Computer Engineering, or Systems Engineering, or equivalent experience.
- 5+ years with hands-on silicon: bring-up, post-silicon speed validation, frequency characterization, or timing analysis on real hardware.
- Strong computer architecture fundamentals including pipeline structures, clocking, memory hierarchies, and how microarchitectural decisions propagate into frequency and power.
- Depth in static timing analysis, critical path identification, and the ability to read and reason about timing reports at the block and chip level.
- Proficiency in silicon margining, guard-banding, and PVT/binning dependencies.
- Scripting depth in Python, Perl, or C/C++.
Skills: silicon speed characterization, post-silicon validation, timing analysis, PVT, critical path, AI agents
This role has been open 82 days — well above the 43-day median for Post-Silicon Validation roles.
Post-Silicon Validation · Silicon Validation
|
Open roles in category
410
|
Median days open
43 d
|
Median salary
$172k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (410 roles · 61 employers) |
|---|---|---|
| Open roles in this specialty | 26 | 410 |
| Open roles in the wider Silicon Validation & Test family | 97 | 2219 · 113 employers |
| Median days open | 25 d | 43 d (−18 d vs this employer) |
| Median salary (USD postings) | — | $172k |
Skills observed across this category: silicon speed characterization, post-silicon validation, timing analysis, PVT, critical path, AI agents
Who's hiring in this category
- AMD · 58 open roles · median 44 d
- Micron Technology · 39 open roles · median 40 d
- Qualcomm · 36 open roles · median 29 d
- NVIDIA (this employer) · 26 open roles · median 24 d
- Microchip Technology · 22 open roles · median 69 d
- Graphcore · 20 open roles · median 122 d
How we counted: 410 open Post-Silicon Validation (Silicon Validation) roles from 61 employers tracked in the SemiconductorJobs index, counted 18 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.