Senior Software Engineer- AI for RTL Design & Formal Verification - San Jose, California, United States
$160,500 - $200,000 USD yearly
Originally posted 31 August 2026 by the employer.
About the role
This role involves developing and deploying AI applications for RTL design, static analysis, and formal verification workflows.
What you'll do
- Design, develop, and deploy AI applications using LLMs and agentic frameworks to support RTL, physical and analog design, static/lint checking, and formal verification flows.
- Build infrastructure to deploy LLM-powered engineering assistants and multi-turn dialogue systems.
- Develop agentic AI solutions for tasks such as RTL rule and lint checking, RTL optimization, bug triage, formal proof convergence, and static verification report analysis.
- Fine-tune and integrate AI solutions with existing CAD/EDA flows.
- Build and maintain design databases and dashboards that combine agentic and deterministic retrieval.
- Collaborate with RTL design, DV, formal verification, and CAD/EDA teams to translate pain points into AI-assisted tooling.
What you'll need
- Bachelor's or Master's degree in Electrical Engineering, Computer Science/Engineering, or equivalent experience.
- 4-10 years of industry experience in software engineering, with direct exposure to RTL design, static/lint verification, or formal verification methodologies.
- Proficiency in Python for rapid prototyping, with strong fundamentals in data structures, algorithms, and software engineering practices.
- Experience with LLMs, including fine-tuning, building multi-agent systems, RAG pipelines, and vector databases.
- Familiarity with RTL design languages (Verilog/SystemVerilog) and formal/static verification tools (e.g., JasperGold, VC Formal, or similar).
Nice to have
- Direct experience applying AI/ML techniques to EDA or CAD flow problems.
- Proficiency in modern software engineering practices, including version control, testing, and CI/CD.
- Experience with formal property verification, assertion-based verification (SVA), or static timing/lint tools.
- A track record of learning across disparate domains (AI/ML and hardware design).
This role has been open 30 days — well below the 61-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
980
|
Median days open
61 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (980 roles · 100 employers) |
|---|---|---|
| Open roles in this specialty | 29 | 980 |
| Open roles in the wider Digital Design & Verification family | 62 | 3112 · 115 employers |
| Median days open | 21 d | 61 d (−40 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 147 open roles · median 55 d
- Synopsys · 67 open roles · median 24 d
- AMD · 62 open roles · median 43 d
- NXP Semiconductors · 51 open roles · median 70 d
- Analog Devices · 46 open roles · median 37 d
- NVIDIA · 46 open roles · median 55 d
How we counted: 980 open Digital/RTL Design (RTL Design) roles from 100 employers tracked in the SemiconductorJobs index, counted 1 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.